Jaya P Samala

6424195, Jul 23, 2002

May 16, 2001

09/859945

Jaya Prakash Samala - San Jose CA

Sun Microsystems, Inc. - Palo Alto CA

H03K 3365

327211, 327210, 327212, 327218, 327225, 327219, 327200

A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data input signal. The first input latch has a first shutoff mechanism and the second input latch has a second shutoff mechanism. During a precharge phase, the first and second input latches each provide an output signal. During an evaluation phase, the first and second input latches sample the data input signal and complemented data input signal if a compare enable signal is activated. The shutoff mechanisms as well will then only activate if the compare enable signal is activated. This allows the circuit to save power because flip-flop will not execute a compare during each clock cycle.

6567944, May 20, 2003

Jul 14, 2000

09/616826

Gajendra P. Singh - Sunnyvale CA
Jaya Prakash Samala - San Jose CA
Sridhar Narayanan - Cupertino CA
Ishwardutt Parulkar - San Francisco CA

Sun Microsystems, Inc. - Palo Alto CA

G01R 3128

714727

A boundary scan cell design which places the multiplexor before the functional flip-flip on the functional line path, reducing the multiplexor delay in the critical path. This optimizes the multiplexor and functional flip-flop orientation, allowing for a significant reduction in the time required from output of the functional flip-flop to a pin or to the interior of the CPU (the clock to q delay). In order to ensure that boundary scan mode functions properly, the functional flip-flop may be designed to act as a buffer, i. e. become transparent, when the boundary scan cell is in boundary scan mode.

6578168, Jun 10, 2003

Jul 14, 2000

09/616825

Ishwardutt Parulkar - San Francisco CA
Sridhar Narayanan - Cupertino CA
Gajendra P. Singh - Sunnyvale CA
Jaya Prakash Samala - San Jose CA

Sun Microsystems, Inc. - Palo Alto CA

G01R 3128

714727

A boundary scan cell design which places the multiplexor before the functional flip-flip on the functional line path, reducing the multiplexor delay in the critical path. This optimizes the multiplexor and functional flip-flop orientation, allowing for a significant reduction in the time required from output of the functional flip-flop to a pin or to the interior of the CPU (the clock to q delay). In order to ensure that boundary scan mode functions properly, the functional flip-flop may be designed to act as a buffer, i. e. become transparent, when the boundary scan cell is in boundary scan mode.

6654893, Nov 25, 2003

Jun 1, 2000

09/586476

Jaya Prakash Samala - San Jose CA

Sun Microsystems, Inc. - Santa Clara CA

G06F 132

713300, 713324

A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data input signal. The first input latch has a first shutoff mechanism and the second input latch has a second shutoff mechanism. During a precharge phase, the first and second input latches each provide an output signal. During an evaluation phase, the first and second input latches sample the data input signal and complemented data input signal if a compare enable signal is activated. The shutoff mechanisms as well will then only activate if the compare enable signal is activated. This allows the circuit to save power because flip-flop will not execute a compare during each clock cycle.

7200793, Apr 3, 2007

Mar 22, 2002

10/106305

Subramani Kengeri - San Jose CA, US
David Walter Carr - Nepean, CA
Paul Nadj - Ottawa, CA
Jaya Prakash Samala - San Jose CA, US

Altera Corporation - San Jose CA

G11C 29/00

714768, 702117, 711108, 711221

Error checking and correcting (ECC) is performed on data held in a content addressable memory. An error check circuit receives words from a memory circuit or circuits, generates an error status and generates a corrected value when appropriate. A control circuit sequences through each of the words of the memory circuit(s), periodically reads from the memory circuit the next word in the sequence and provides the next word to the error check circuit. The bandwidth consumed by the periodic error check phase can be controlled by adjusting the interval between reads.

6288932, Sep 11, 2001

Jun 1, 2000

9/586477

Jaya Prakash Samala - San Jose CA

SUN Microsystems, Inc. - Palo Alto CA

G11C 1100

365154

A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data input signal. The first input latch has a first shutoff mechanism and the second input latch has a second shutoff mechanism. During a precharge phase, the first and second input latches each provide an output signal. During an evaluation phase, the first and second input latches sample the data input signal and complemented data input signal if a compare enable signal is activated. The shutoff mechanisms as well will then only activate if the compare enable signal is activated. This allows the circuit to save power because flip-flop will not execute a compare during each clock cycle.