Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 513
Abstract:
A driver circuit for generating non-overlapping clocking signals. A single clocking source is divided down into two clock signals which are passed through a plurality of inverter delay chains to insure non-overlapping output signals. Inverters made up of CMOS transistors having long channel lengths are utilized in order to eliminate overlap between the clock signals. Inverter delay chains are also utilized to prevent skewing between a true clock output signal and its complement.