James H Stefany

48871354, Dec 12, 1989

Jan 24, 1985

6/694487

Glen T. Cheney - Allentown PA
Howard C. Kirsch - Colorado Springs CO
James T. Nelson - Coopersburg PA
James H. Stefany - Asbury NJ

American Telephone and Telegraph Company, AT&T Bell Laboratories - Murray Hill NJ

H01L 2978
H01L 2702
H01L 2710
H01L 2904

357 236

A self-aligned one transistor-capacitor memory cell is provided which uses an n-channel MOS transistor having separate drain and source regions with a first level polysilicon conductor coupled to the top plate of the capacitor and separate second level polysilicon conductors coupled to the gate and drain of the transistor. A reduction in a dimension of the memory cell is acheived compared to a similar memory cell which uses only one level of conductors.

46495231, Mar 10, 1987

Feb 8, 1985

6/699661

Clinton H. Holder - Catasauqua PA
Howard C. Kirsch - Emmaus PA
James H. Stefany - Asbury NJ

AT&T Bell Laboratories - Murray Hill NJ

G11C 700

365203

A dynamic random access memory has a row conductor boosted in excess of the power supply level during an initial portion of a memory cycle. The voltage is then clamped at the supply level during the middle portion of the cycle, and optionally boosted again during the refresh portion. This allows improved performance and reliability, especially in memories employing bit lines precharged to one-half the power supply level.

45831572, Apr 15, 1986

Feb 8, 1985

6/699794

Howard C. Kirsch - Emmaus PA
James H. Stefany - Asbury NJ

AT&T Bell Laboratories - Murray Hill NJ

H02M 318
H03K 502

363 60

An integrated circuit comprises a node that is boosted by one or more boost capacitors depending on the level of the power supply voltage. When the level is below a given threshold, a first booster capacitor is activated. Additional boost capacitors may be provided for activation at still lower thresholds. The boost capacitors are deactivated when the power supply level exceeds the corresponding thresholds. In this manner, a more constant boosted voltage is obtained. This provides for an adequate boosted voltage at low power supply levels, while avoiding excessive boost at high power supply voltages that could damage devices. The technique may be used for boosted row conductors in dynamic random access memories, among other applications.