Inventors:
Juan A. Chediak - Berkeley CA
Randy W. Mann - Jericho VT
James A. Slinkman - Montpelier VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2972
US Classification:
257401, 257252, 257332, 257346, 257382, 257384, 257393, 257412
Abstract:
A method of forming conductive contacts to drain and source regions of a semiconductor device such as a field effect transistor (FET). A gate structure is formed over a portion of a semiconductor substrate, wherein the gate structure includes: a gate dielectric on a surface of the semiconductor substrate, a conductive gate aligned on the gate dielectric, a silicide layer aligned on the conductive gate, and a silicon nitride cap aligned on the silicide layer. Insulative spacers are formed on sidewalls of the gate structure, and the insulative spacers contact the semiconductor substrate. A drain region and a source region are formed within the semiconductor substrate, wherein a channel region is disposed between the drain region and the source region, and wherein the gate structure is over the channel region. After an insulative region containing a photosensitive material, such as boro-phoso-silicate glass, is formed over the gate structure and the semiconductor substrate, a cavity over the drain region and a cavity over the source region are formed photolithographically. The cavities are filled with conductive material such as tungsten, forming a conductive contact to the drain region and a conductive contact to the source region.
