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James Meindl Phones & Addresses

  • Greensboro, GA
  • Los Altos, CA
  • 1046 Woodruff Plantation Ct SE, Marietta, GA 30067 (770) 850-9469 (770) 933-9214
  • Troy, NY
  • 1521 Jackson Ridge Rd, Greensboro, GA 30642 (706) 467-9040

Education

Degree: High school graduate or higher

Business Records

Name / Title
Company / Classification
Phones & Addresses
James Meindl
Director
Sandisk Corporation
Mfg Computer Storage Devices
601 Mccarthy Blvd, Milpitas, CA 95035
(408) 801-1000
James Meindl
Director
U.S. Venture Partners
Venture Capital & Private Equity · Security Brokers and Dealers, Nsk · Financial Management for Businesses · Portfolio Management · Open-End Investment Funds
2735 Sand Hl Rd, Menlo Park, CA 94025
2180 Sand Hl Rd, Menlo Park, CA 94025
(650) 854-9080, (650) 854-3018, (650) 926-7715
James Meindl
Director
SanDisk
Semiconductors · Manufacturing · Computer and Electronic Product Manufacturing · Computer and Peripheral Equipment Mfg. · Wholesale Of Flash Memory · Management Consulting Services · Mfg Computer Storage Devices · Computer Storage Devices
951 Sandisk Dr, Milpitas, CA 95035
Rose Roachell, Milpitas, CA 95035
2390 E Camelback Rd, Phoenix, AZ 85016
601 Mccarthy Blvd, Milpitas, CA 95035
(408) 801-1000, (408) 944-9450, (408) 801-1310, (408) 801-1743

Publications

Wikipedia

James D. Meindl

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James D. Meindl (born April 20, 1933) is director of the Joseph M. Pettit Microelectronics Research Center, director of the Marcus Nanotechnology Research Center, and Pettit Chair ...

Us Patents

Monolithically-Fabricated Compliant Wafer-Level Package With Wafer Level Reliability And Functionality Testability

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US Patent:
6528349, Mar 4, 2003
Filed:
Oct 26, 2000
Appl. No.:
09/697031
Inventors:
Chirag S. Patel - Peekskill NY
Kevin Martin - Atlanta GA
James D. Meindl - Marietta GA
Assignee:
Georgia Tech Research Corporation - Atlanta GA
International Classification:
H01L 2144
US Classification:
438117, 438 15, 438106, 438108, 438612, 438613, 438623, 438624, 438640
Abstract:
Compliant wafer level packages and methods for monolithically fabricating the same. A monolithically fabricated compliant wafer level package having a compliant layer and a compliant interconnect passing therein. The compliant interconnects being provided so that electrical and mechanical connections may be supported across the compliant layer , and constructed so that stresses related to relative motion between electrical components is accommodated. A method of providing a substrate having a compliant layer , the compliant layer having a via that exposes a die pad on the substrate. Fabricating a compliant interconnect so that the compliant interconnect contacts the die pad. The compliant interconnect constructed so that electrical and mechanical connections may be supported through the compliant layer.

Phase Mask Consisting Of An Array Of Multiple Diffractive Elements For Simultaneous Accurate Fabrication Of Large Arrays Of Optical Couplers And Method For Making Same

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US Patent:
6606432, Aug 12, 2003
Filed:
May 3, 2001
Appl. No.:
09/848935
Inventors:
Thomas K. Gaylord - Atlanta GA
Elias N. Glytsis - Atlanta GA
James D. Meindl - Marietta GA
Assignee:
Georgia Tech Research Corp. - Atlanta GA
International Classification:
G02B 634
US Classification:
385 37, 359 12
Abstract:
The present invention entails a phase mask for producing a plurality of volume gratings for use as optical couplers and method for creating the phase mask. The phase mask is produced by creating a plurality of volume gratings having predetermined characteristics which allow the phase mask, when excited by a coherent light wave, to produce a plurality of volume gratings in a recording material.

Compliant Wafer-Level Packaging Devices And Methods Of Fabrication

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US Patent:
6690081, Feb 10, 2004
Filed:
Nov 19, 2001
Appl. No.:
09/993100
Inventors:
Muhannad S. Bakir - Atlanta GA
Hollie Reed - Atlanta GA
Paul Kohl - Atlanta GA
Chirag S. Patel - Peekskill NY
Kevin P. Martin - Atlanta GA
James Meindl - Marietta GA
Assignee:
Georgia Tech Research Corporation - Atlanta GA
International Classification:
H01L 2900
US Classification:
257522, 257792, 257506, 438461, 438421
Abstract:
Devices and method of fabrication thereof are disclosed. A representative device includes one or more lead packages. The lead packages include a substrate including a plurality of die pads, an overcoat polymer layer, a plurality of sacrificial polymer layers disposed between the substrate and the overcoat polymer layer, and a plurality of leads. Each lead is disposed upon the overcoat polymer layer having a first portion disposed upon a die pad. The sacrificial polymer layer can be removed to form one or more air-gaps.

Guided-Wave Optical Interconnections Embedded Within A Microelectronic Wafer-Level Batch Package

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US Patent:
6785458, Aug 31, 2004
Filed:
Feb 11, 2002
Appl. No.:
10/074420
Inventors:
Chirag Patel - College Park GA
James D. Meindl - Marietta GA
Thomas K. Gaylord - Atlanta GA
Elias N. Glytsis - Dunwoody GA
Kevin P. Martin - Atlanta GA
Stephen M. Schultz - Tucson AZ
Muhannad Bakir - Atlanta GA
Hollie Reed - Smyrna GA
Paul Kohl - Atlanta GA
Assignee:
Georgia Tech Research Corporation - Atlanta GA
International Classification:
G02B 610
US Classification:
385131, 385132
Abstract:
Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.

Backplane, Printed Wiring Board, And/Or Multi-Chip Module-Level Optical Interconnect Layer Having Embedded Air-Gap Technologies And Methods Of Fabrication

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US Patent:
6788867, Sep 7, 2004
Filed:
Dec 11, 2003
Appl. No.:
10/734075
Inventors:
James D. Meindl - Marietta GA
Paul Kohl - Atlanta GA
Stephen M. Schultz - Tucson AZ
Thomas K. Gaylord - Atlanta GA
Elias N. Glytsis - Dunwoody GA
Ricardo Villalaz - Atlanta GA
Muhannad Bakir - Atlanta GA
Hollie Reed - Smyrna GA
Assignee:
Georgia Tech Research Corp. - Atlanta GA
International Classification:
G02B 600
US Classification:
385129, 385 14, 385130, 385132
Abstract:
Optical interconnect layers and methods of fabrication thereof are described. In addition, the optical interconnect layers integrated into devices such as backplane (BP), printed wiring board (PWB), and multi-chip module (MCM) level devices are described. A representative optical interconnect layer includes a first cladding layer, a second cladding layer, one or more waveguides having a waveguide core and an air-gap cladding layer engaging a portion of waveguide core, wherein the first cladding layer and the second cladding layer engage the waveguide.

Optical Waveguides With Embedded Air-Gap Cladding Layer And Methods Of Fabrication Thereof

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US Patent:
6807352, Oct 19, 2004
Filed:
Feb 11, 2002
Appl. No.:
10/074067
Inventors:
James D. Meindl - Marietta GA
Thomas K. Gaylord - Atlanta GA
Elias N. Glytsis - Dunwoody GA
Paul Kohl - Atlanta GA
Assignee:
Georgia Tech Research Corporation - Atlanta GA
International Classification:
G02B 610
US Classification:
385131, 385132
Abstract:
Waveguides having air-gap cladding layers and methods of fabricating waveguides having air-gap cladding layers are disclosed. A representative waveguide includes a waveguide core having an air-gap cladding layer engaging a portion of the waveguide core. In addition, a representative method of fabricating a waveguide having an air-gap cladding layer includes: providing a substrate having a lower cladding layer disposed on the substrate; disposing a waveguide core on a portion of the lower cladding layer; disposing a sacrificial layer onto at least one portion of the lower cladding layer and the waveguide core; disposing an overcoat layer onto the lower cladding layer and the sacrificial layer; and removing the sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and engaging a portion of the waveguide core.

Optical Waveguides Formed From Nano Air-Gap Inter-Layer Dielectric Materials And Methods Of Fabrication Thereof

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US Patent:
6947651, Sep 20, 2005
Filed:
May 10, 2002
Appl. No.:
10/142601
Inventors:
Paul Kohl - Atlanta GA, US
James D. Meindl - Marietta GA, US
Agnes Padovani - Phoenix AZ, US
Thomas K. Gaylord - Atlanta GA, US
Elias N. Glytsis - Dunwoody GA, US
Sue Ann B. Allen - Atlanta GA, US
Assignee:
Georgia Tech Research Corporation - Atlanta GA
International Classification:
G02B006/02
G02B006/20
US Classification:
385125
Abstract:
Waveguides and methods of fabrication thereof are presented. A representative waveguide includes a waveguide core and a cladding layer, where the cladding layer surrounds the waveguide core. The waveguide core and cladding can be made of a host material having a plurality of nano-pores, wherein the nano-pores include a sacrificial material, and the sacrificial material can be selectively decomposed in both the core and cladding layers to form a plurality of nano air-gaps.

Guided-Wave Optical Interconnections Embedded Within A Microelectronic Wafer-Level Batch Package

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US Patent:
6954576, Oct 11, 2005
Filed:
Jul 21, 2004
Appl. No.:
10/895685
Inventors:
Chirag Patel - College Park GA, US
James D. Meindl - Marietta GA, US
Thomas K. Gaylord - Atlanta GA, US
Elias N. Glytsis - Dunwoody GA, US
Kevin P. Martin - Atlanta GA, US
Stephen M. Schultz - Tucson AZ, US
Muhannad Bakir - Atlanta GA, US
Hollie Reed - Smyrna GA, US
Paul Kohl - Atlanta GA, US
Assignee:
Georgia Tech Research Corporation - Atlanta GA
International Classification:
G02B006/10
US Classification:
385131, 438 31
Abstract:
Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.

Isbn (Books And Publications)

Cognition Within and Between Organizations

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Author

James R. Meindl

ISBN #

0761901132

Cognition Within and Between Organizations

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Author

James R. Meindl

ISBN #

0761901140

Grounding Leadership Theory and Research: Issues and Perspectives and Methods

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Author

James R. Meindl

ISBN #

1931576009

Grounding Leadership Theory and Research: Issues and Perspectives and Methods

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Author

James R. Meindl

ISBN #

1931576017

Micropower Circuits

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Author

James D. Meindl

ISBN #

0471591572

Brief Lessons in High Technology: A Primer on Seven Fields That Are Changing Our Lives

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Author

James D. Meindl

ISBN #

0916318419

James D Meindl from Greensboro, GADeceased Get Report