James David Gallia

6563158, May 13, 2003

Nov 16, 2001

10/039810

Theodore W. Houston - Richardson TX
James D. Gallia - McKinney TX

Texas Instruments Incorporated - Dallas TX

H01L 27108

257296, 257300, 257301

An integrated circuit includes several circuit portions coupled between two rails that carry respective different voltage potentials. Each circuit portion includes a relatively small capacitance, coupled in series with a resistance which is sufficient to effect substantial limiting of the magnitude of any leakage current that may flow through the capacitor.

6708303, Mar 16, 2004

Feb 26, 1999

09/259004

James D. Gallia - Dallas TX

Texas Instruments Incorporated - Dallas TX

G01R 3128

714726, 326 16

A scan circuit ( ) has a scan data input ( ), a normal data input ( ), a clock input ( ), a scan enable input ( ), a normal data output ( ), and a scan data output ( ). The scan circuit includes a multiplexer ( ) having two data inputs respectively coupled to the scan data input and normal data input of the scan circuit, having a control input coupled to the scan enable input of the scan circuit, and having an output. The scan circuit also includes a D-type flip-flop ( ) having a data input coupled to the output of the multiplexer, having a clock input coupled to the clock input of the scan circuit, and having a data output serving as the normal data output of the scan circuit. The scan circuit further includes a gate ( ) having a first input coupled to an output of the flip-flop, having a second input coupled to the scan enable input of the scan circuit, and having an output which serves as the scan data output of the scan circuit.

6870375, Mar 22, 2005

Jul 1, 2002

10/187671

Robin C. Sarma - Plano TX, US
Xiaowei Deng - Plano TX, US
James David Gallia - McKinney TX, US

Texas Instruments Incorporated - Dallas TX

G01R027/26

324658, 324678

A method for measuring a capacitance associated with a portion of an integrated circuit is provided that includes coupling a measurement circuit to an integrated circuit. One or more transistors within the integrated circuit are initialized such that a steady-state associated with one or more of the transistors is achieved. A capacitance associated with the portion of the integrated circuit is then measured using the measurement circuit. The portion of the integrated circuit is selectively charged and discharged in response to a voltage potential being applied thereto such that a drain current is generated that serves as a basis for the capacitance measurement.

7638412, Dec 29, 2009

Jul 24, 2007

11/782523

James D. Gallia - McKinney TX, US
Srikanth Krishnan - Richardson TX, US
Anand T. Krishnan - Farmers Branch TX, US

Texas Instruments Incorporated - Dallas TX

H01L 21/20
H01L 21/36
H01L 21/302
H01L 21/461

438479, 438689, 438707, 438710, 257E21352

According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.

7262468, Aug 28, 2007

Dec 28, 2001

10/035606

James D. Gallia - McKinney TX, US
Srikanth Krishnan - Richardson TX, US
Anand T. Krishnan - Richardson TX, US

Texas Instruments Incorporated - Dallas TX

H01L 23/62
H01L 27/01
H01L 27/02
H01L 31/0392

257356, 257349, 257350, 257355

According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.

20030122123, Jul 3, 2003

Dec 31, 2001

10/039484

Xiaowei Deng - Plano TX, US
James Gallia - McKinney TX, US

Texas Instruments Incorporated

H01L023/58

257/048000

A method of determining a capacitance for use in a circuit simulation is provided. The method may include determining a test structure capacitance of a test structure, simulating a design structure, extracting a design structure capacitance of the simulated design structure, and calculating a parasitic capacitance of the design structure. Calculating the parasitic capacitance may comprise deducting the test structure capacitance from the design structure capacitance.

51736233, Dec 22, 1992

Feb 27, 1992

7/842801

Kwok K. Chau - Dallas TX
James D. Gallia - Dallas TX
Ashwin H. Shah - Dallas TX

Texas Instruments Incorporated - Dallas TX

H03K 1902
H03K 1760
H03K 301
H03K 19094

307446

BiCMOS circuits are disclosed which achieve high speed operation under a wide range of loading conditions. The circuits are capable of providing a full output voltage swing and dissipate virtually no static power. The BiCMOS circuits are implemented using both CMOS and bipolar transistors. The circuits use their output signal to control the CMOS transistors that overcome bipolar output drops for full swing operation. The same fundamental CMOS and bipolar configurations can be applied to implement complex and simple logic functions such as NAND, NOR, AND, or OR operations.

51071479, Apr 21, 1992

Mar 28, 1991

7/677001

James D. Gallia - Dallas TX

Texas Instruments Incorporated - Dallas TX

H03K 19177

3074651

A BiCMOS gate array base is disclosed which is capable of simultaneously implementing a BiCMOS gate and/or a multitude of CMOS gates. The cell has symmetry about 1 axis, with the bipolar devices in the center and equally accessible for interconnect by two CMOS sections. The cell allows half-cell macro circuit blocks to be placed into the base cell in an independent and flexible fashion. The same macro can be placed in either CMOS section because of the mirror symmetry. The base cell can be divided into 2 units of macro placement. The number of devices in the CMOS section is variable. This cell architecture can be extended to other mixed technologies.