James H Ewertz

6499102, Dec 24, 2002

Dec 29, 1999

09/474219

James H. Ewertz - Portland OR

Intel Corporation - Santa Clara CA

G06F 132

713 1, 713320

A computer systems BIOS (basic input/output system) POST (power-on self test) sets a bit or bits in an ISA (industry standard architecture) I/O (input/output) port, in a memory, or in a scratch pad register accessed via an ISA I/O port (indexed or non-indexed), that an AML (ACPI control method machine language) in the DSDT or other ACPI tables can access. These bit(s) will be set depending upon SETUP program selections or different hardware configurations detected by the BIOS during POST. The AML, which is the compiled result of ASL (ACPI control method Source Language) code, returns back different values for the lowest system sleep state depending upon the bit value(s) read from the ISA I/O port, the memory or the scratch pad register accessed via the ISA I/O port. In addition, an ASL code allows an external agent, e. g. , an application program, to modify the ISA I/O port, the memory or the scratch pad register accessed via the ISA I/O port.

6536038, Mar 18, 2003

Nov 29, 1999

09/450832

James H. Ewertz - Portland OR
Robert P. Hale - Portland OR
Orville H. Christeson - Portland OR

Intel Corporation - Santa Clara CA

G06F 944

717168, 717169, 713 1, 713 2, 713100, 711 1, 711102, 711103, 711104, 711105, 711170

A method for updating firmware. The method includes providing replaceable information in a non-modifiable storage and replacement information in a modifiable storage or a removable storage and providing a replacement indicator. The replacement information is accessed instead of the replaceable information based upon the replacement indicator.

6718461, Apr 6, 2004

Apr 28, 2000

09/560454

James H. Ewertz - Portland OR

Intel Corporation - Santa Clara CA

G06F 15177

713 1, 713 2, 710 10

A processor-based system may selectively undergo one of two power on self test routines. The determination as to whether to undergo the full power on self routine or an abbreviated routine is based on whether or not the user has opened the chassis of the computer system. If the chassis has not been opened, one may assume the components of the system have not been altered and an abbreviated post is used because all the components need not be testing during the boot process.

6725384, Apr 20, 2004

Jun 30, 2000

09/607335

John P. Lambino - Beaverton OR
James H. Ewertz - Portland OR

Intel Corporation - Santa Clara CA

G06F 126

713320, 713300, 713310, 713322, 713323, 713324

A method and apparatus provides hardware-configured wake-up events for a computer operating system compliant with an advanced configuration and power interface (ACPI) protocol without requiring additional hardware. The method and apparatus includes generation of a system management interrupt (SMI) during normal ACPI working-to-sleep transition allowing a basic input-output system (BIOS) circuit to enable additional wake-up events independent of the computer operating system.

54796393, Dec 26, 1995

Aug 26, 1994

8/279692

James H. Ewertz - Portland OR
Orville H. Christeson - Portland OR
Douglas L. Gabel - Aloha OR
Sean T. Murphy - Portland OR

Intel Corporation - Santa Clara CA

G06F 1202

395430

A computer system wherein a paging technique is used to expand the useable non-volatile memory capacity beyond a fixed address space limitation. The computer system of the preferred embodiment includes a flash memory component for storing non-volatile code and data including a system BIOS in the upper 128K of memory. The useful BIOS memory space is effectively increased while maintaining the address boundary of the upper 128K region. The address space of the non-volatile memory device is logically separated into distinct pages of memory (Pages 1-4). Using the apparatus and techniques of the present invention, Page 1, Page 3 and Page 4 may be individually swapped into the address space originally occupied by Page 1 (the swappable page area). In the preferred embodiment, Page 2 is held static and thus is not used as a swap area. Each of the swappable pages, Page 1, Page 3, and Page 4, contain processing logic called swapping logic used during the swapping or paging operation.

53718763, Dec 6, 1994

Oct 14, 1993

8/137376

James H. Ewertz - Portland OR
Orville H. Christeson - Portland OR
Douglas L. Gabe - Aloha OR
Sean T. Murphy - Portland OR

Intel Corporation - Santa Clara CA

G06F 1202

395425

A computer system wherein a paging technique is used to expand the usable non-volatile memory capacity beyond a fixed address space limitation. The computer system of the preferred embodiment includes a flash memory component for storing non-volatile code and data including a system BIOS in the upper 128K of memory. The useful BIOS memory space is effectively increased while maintaining the address boundary of the upper 128K region. The address space of the non-volatile memory device is logically separated into distinct pages of memory (Pages 1-4). Page 1, Page 3 and Page 4 may be individually swapped into the address space originally occupied by Page 1 (the swappable page area). In the preferred embodiment, Page 2 is held static and thus is not used as a swap area. Each of the swappable pages contain processing logic called swapping logic used during the swapping or paging operation. The swapping logic operates in conjunction with paging hardware to effect the swapping of pages into the swappable page area.