James W Elmer

20040046961, Mar 11, 2004

Sep 6, 2002

10/236226

Colin Yates - Clackamas OR, US
James Elmer - Vancouver WA, US

G01B011/00

356/401000

A method for characterizing overlay errors between at least a first and a second mask layer for an integrated circuit. A first primary alignment structure is formed in a first position of the inter-layer region around the first mask layer, and a first secondary alignment structure is formed in a second position of the inter-layer region around the first mask layer. Similarly, a second primary alignment structure is formed in a first position of an inter-layer region around the second mask layer, and a second secondary alignment structure is formed in a second position of the inter-layer region around the second mask layer. The first mask layer and the second mask layer are exposed onto a photoresist coated substrate with a first exposure and a second exposure, where the first position of the first primary alignment structure during the first exposure generally aligns with the second position of the second secondary alignment structure, and the second position of the first secondary alignment structure during the second exposure generally aligns with the first position of the second primary alignment structure. The photoresist on the substrate is developed, and offsets between the first primary alignment structure and the second secondary alignment structure are measured, and offsets between the second primary alignment structure and the first secondary alignment structure are also measured, to determine the overlay errors.

20050064716, Mar 24, 2005

Sep 28, 2004

10/951646

Hong Lin - Vancouver WA, US
Shiqun Gu - Vancouver WA, US
Wai Lo - Lake Oswego OR, US
James Elmer - Vancouver WA, US

H01L029/80
H01L031/112
H01L021/302
H01L021/461

438709000, 438710000

A method of forming a high k gate insulation layer in an integrated circuit on a substrate. A high k layer is deposited onto the substrate, and patterned with a mask to define the high k gate insulation layer and exposed portions of the high k layer. The exposed portions of the high k layer are subjected to an in-situ plasma species that causes structural damage to the exposed portions of the high k layer. The structurally damaged exposed portions of the high k layer are wet etched to leave the high k gate insulation layer.

20050078289, Apr 14, 2005

Dec 1, 2004

11/000772

David Daniel - Vancouver WA, US
James Elmer - Vancouver WA, US

G03B027/42

355053000

An integrated circuit substrate having a first surface for receiving a series of aligned layers during the creation of the integrated circuit, and a second surface disposed substantially opposite the first surface, where the second surface has at least one alignment mark for aligning the series of aligned layers one to another during the creation of the integrated circuit. In another aspect the invention provides for an apparatus for aligning a mask having an image and at least one complimentary alignment mark to a substrate having a first surface and a substantially opposing second surface. The substrate further has at least one alignment mark on the second surface. A mask support supports the mask in proximity to the first surface of the substrate. A substrate support supports the substrate with the first surface in proximity to the mask. An alignment means aligns the at least one alignment mark on the second surface of the substrate to the at least one complimentary alignment mark on the mask. An exposure source projects the image of the mask onto the first surface of the substrate, and a controller controls the mask support, substrate support, alignment means, and exposure source. In yet another aspect, the invention provides for a method for aligning a mask having an image and at least one complimentary alignment mark to a substrate having a first surface and a substantially opposing second surface. The substrate also has at least one alignment mark on the second surface. A mask is disposed in proximity to the first surface of the substrate. An image of the at least one alignment mark is created, as is an image of the at least one complimentary alignment mark. At least one of the mask and substrate is moved relative to the other, and the image of the least one alignment mark is aligned to the image of the at least one complimentary alignment mark. The image of the mask is projected onto the first surface of the substrate.

20050181615, Aug 18, 2005

Mar 4, 2005

11/072127

Peter Burke - Portland OR, US
Eric Kirchner - Troutdale OR, US
James Elmer - Vancouver WA, US

H01L021/76
H01L021/302

438691000, 438692000, 438424000

A method for monitoring polishing process parameters for an integrated circuit structure on a substrate. A first metrology site is constructed on the substrate. The first metrology site represents a design extreme of a high density integrated circuit structure. The first metrology site is formed by placing a relatively small horizontal surface area trench within a relatively large surface area field of a polish stop material. A second metrology site is also constructed on the substrate. The second metrology site represents a design extreme of a low density integrated circuit structure. The second metrology site is formed by placing a relatively large horizontal surface area trench within a relatively small surface area field of a polish stop material. The substrate is covered with a layer of an insulating material, thereby at least filling the trenches. A target thickness of the insulating material necessary to leave the trenches substantially filled to a top surface of the field of polish stop material is calculated. The substrate is polished until a first thickness of the insulating material in the trench of the first metrology site is no more than the target thickness. A second thickness of the insulating material in the trench of the second metrology site is measured, and values based on the first thickness and the second thickness are monitored as the polishing process parameters for the integrated circuit structure.

20060281256, Dec 14, 2006

Dec 20, 2005

11/312849

Richard Carter - Vancouver WA, US
Hemanshu Bhatt - Vancouver WA, US
Shiqun Gu - Vancouver WA, US
Peter Burke - Portland OR, US
James Elmer - Vancouver WA, US
Verne Hornback - Camas WA, US

H01L 21/336

438260000

A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.

20060292716, Dec 28, 2006

Jan 11, 2006

11/329849

Shiqun Gu - Vancouver WA, US
James Elmer - Vancouver WA, US
Peter Burke - Portland OR, US

H01L 21/00

438020000

Disclosed is a method of making a CNT device such as a memory switch, a field emission display, interconnect wiring, etc. The method includes steps of providing CNTs in contact with an electrode and selectively growing or depositing a layer of metal on top of the CNTs and the electrode. The layer of metal improves the electrical contact between the CNTs and the electrode. If a CNT memory switch is provided, the electrode can be embedded into dielectric or may lie on top of a dielectric substrate. In the case of interconnect wiring, an electrode can be provided embedded in dielectric and a via may be provided to the electrode. CNTs are disposed in the via, and the method provides that metal is selectively grown or deposited in the via, in contact with the CNTs and the electrode, thereby providing good electrical contact between the CNTs and the electrode.