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Jaideep Mavoori

from Mercer Island, WA
Age ~55
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Also known as:
Jaideep Kovoor
Phone and address:
8740 SE 48Th St, Mercer Island, WA 98040
Related to:
Suzanna Mavoori, 52Abraham Kovoor, 56
Connected to:
Anne S Mavor, 87Carol J Mavor, 66James A Mavor, 73Joan B Mavor, 84John H Mavor, 65Jean Mavoucheka, 40Michael P Mavraganes, 47Valmira Mavraj, 40Gary M Mavrakis, 72Gregory H Mavrakis, 55

Jaideep Mavoori Phones & Addresses

  • 8740 SE 48Th St, Mercer Island, WA 98040
  • 16659 26Th St, Bellevue, WA 98008
  • 7001 Old Redmond Rd, Redmond, WA 98052
  • 7010 151St Ave NE, Redmond, WA 98052
  • 109 Regency Dr, Central, SC 29630
  • 1104 Eastview Cir, Richardson, TX 75081 (972) 437-9513
  • Clemson, SC
  • Dallas, TX
  • Sunnyvale, CA

Industries

Medical Devices

Resumes

Resumes

Jaideep Mavoori Photo 1

Jaideep Mavoori

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Location:
Greater Seattle Area
Industry:
Medical Devices

Publications

Us Patents

Shallow Trench Isolation Planarization Using Self Aligned Isotropic Etch

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US Patent:
6686283, Feb 3, 2004
Filed:
Feb 4, 2000
Appl. No.:
09/498083
Inventors:
Shawn T. Walsh - Richardson TX
John E. Campbell - Plano TX
Somit Joshi - Dallas TX
James B. Friedmann - Dallas TX
Michael J. McGranaghan - Dallas TX
Janice D. Makos - McKinney TX
Arun Sivasothy - Dallas TX
Troy A. Yocum - Plano TX
Jaideep Mavoori - Richardson TX
Wayne A. Bather - Plano TX
Joe G. Tran - Irving TX
Michelle L. Hartsell - Plano TX
Gregory B. Shinn - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2176
US Classification:
438690, 438691, 438692
Abstract:
A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed to remove material above unetched portions of the substrate. The exposed fill material is etched and planarized to form a planar isolation structure.

Semiconductor With A Nitrided Silicon Gate Oxide And Method

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US Patent:
6716695, Apr 6, 2004
Filed:
Dec 20, 2002
Appl. No.:
10/326188
Inventors:
Sunil V. Hattangady - McKinney TX
Jaideep Mavoori - Redmond WA
Che-Jen Hu - Plano TX
Rajesh B. Khamankar - Coppell TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 218242
US Classification:
438240, 438197, 438591, 438585, 438770, 438775
Abstract:
A method of fabricating a transistor includes providing a semiconductor substrate having a surface and forming a nitride layer outwardly of the surface of the substrate. The nitride layer is oxidized to form a nitrided silicon oxide layer comprising an oxide layer beneath the nitride layer. A high-K layer is deposited outwardly of the nitride layer, and a conductive layer is formed outwardly of the high-K layer. The conductive layer, the high-K layer, and the nitrided silicon oxide layer are etched and patterned to form a gate stack. Sidewall spacers are formed outwardly of the semiconductor substrate adjacent to the gate stack, and source/drain regions are formed in the semiconductor substrate adjacent to the sidewall spacers.

Circuit For Classifying Signals

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US Patent:
7525349, Apr 28, 2009
Filed:
Aug 14, 2006
Appl. No.:
11/504390
Inventors:
Jaideep Mavoori - Bellevue WA, US
Chris Diorio - Seattle WA, US
Assignee:
University of Washington - Seattle WA
International Classification:
H03K 5/22
US Classification:
327 74, 327 75, 324 7683
Abstract:
A circuit for classification of analog input signals, comprising an analog memory component, such as a floating gate, used to store a threshold value; a threshold detection module used to determine whether the analog input signal exceeds the threshold value; a time delay module used to delay a processing of the analog signal; a time-amplitude window calculation module used to determine whether an amplitude of the analog input signal is between a lower limit and an upper limit of an amplitude window; and an output module indicating whether the amplitude of the analog signal is between the lower and the upper limit, wherein the indication is used to determine whether the analog input signal belongs to one of a plurality of analog signal classes. The classification is implemented in the analog domain, eliminating the need for sampling and digitizing the analog signal, consequently minimizing circuit area and power.

Minimally Invasive System For Selecting Patient-Specific Therapy Parameters

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US Patent:
7676263, Mar 9, 2010
Filed:
Jun 21, 2007
Appl. No.:
11/766760
Inventors:
John F. Harris - Bellevue WA, US
Kent W. Leyde - Sammamish WA, US
Jaideep Mavoori - Bellevue WA, US
Assignee:
NeuroVista Corporation - Seattle WA
International Classification:
A61B 5/00
US Classification:
600544
Abstract:
The present invention provides systems and methods for ambulatory, long term monitoring of a physiological signal from a patient. At least a portion of the systems of the present invention may be implanted within the patient in a minimally invasive manner. In preferred embodiments, brain activity signals are sampled from the patient and are transmitted to a handheld patient communication device for further processing.

Schottky Junction Diode Devices In Cmos

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US Patent:
7732887, Jun 8, 2010
Filed:
Mar 22, 2006
Appl. No.:
11/387603
Inventors:
Yanjun Ma - Bellevue WA, US
Ronald A. Oliver - Seattle WA, US
Todd E. Humes - Shoreline WA, US
Jaideep Mavoori - Bellevue WA, US
Assignee:
Virage Logic Corporation - Fremont CA
International Classification:
H01L 31/07
US Classification:
257471, 257371, 257E29265, 257E21053, 257472
Abstract:
A Schottky junction diode device having improved performance is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped to a second conductivity type opposite that of the first conductivity type. A region of metal-containing material is disposed over the first well to form a Schottky junction at an interface between the region of metal-containing material and the first well. In one embodiment, a first well contact is disposed in a portion of the first well. A second well is disposed over the substrate wherein the second well includes a material doped to the first conductivity type. In one embodiment, the first well and the second well are not in direct contact with one another.

Radio Frequency Identification Device Electrostatic Discharge Management

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US Patent:
7843032, Nov 30, 2010
Filed:
Dec 27, 2007
Appl. No.:
11/965307
Inventors:
Cong Khieu - San Jose CA, US
Yanjun Ma - Bellvue WA, US
Jaideep Mavoori - Bellevue WA, US
Assignee:
Synopsis, Inc. - Mountain View CA
International Classification:
H01L 21/82
US Classification:
257499, 257367, 257122, 257E2904
Abstract:
Apparatus, systems, and methods may include managing electrostatic discharge events in radio frequency identification (RFID) devices by using a semiconductor circuit having a non-aligned gate to implement a snap-back voltage protection mechanism. Such circuits may be formed by doping a semiconductor substrate to form a first conductive region as a well, forming one of a source region and a drain region in the well, depositing a layer of polysilicon on the substrate to establish a gating area that does not overlap the one of the source region and the drain region, and forming an integrated circuit including an RFID circuit that is supported by the substrate to couple to the one of the source region and the drain region to provide snap-back voltage operation at a node between the integrated circuit and the source or drain region. Additional apparatus, systems, and methods are disclosed.

Electrostatic Discharge Management Apparatus, Systems, And Methods

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US Patent:
8022498, Sep 20, 2011
Filed:
Aug 13, 2007
Appl. No.:
11/837810
Inventors:
Cong Khieu - San Jose CA, US
Yanjun Ma - Seattle WA, US
Jaideep Mavoori - Bellevue WA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
H01L 29/00
US Classification:
257499, 257E29529
Abstract:
Apparatus, systems, and methods may include managing electrostatic discharge events by using a semiconductor device having a non-aligned gate to implement a snap-back voltage protection mechanism. Such devices may be formed by doping a semiconductor substrate to form a first conductive region as a well, forming one of a source region and a drain region in the well, depositing a layer of polysilicon on the substrate to establish a gating area that does not overlap the one of the source region and the drain region, and forming an integrated circuit supported by the substrate to couple to the one of the source region and the drain region to provide snap-back voltage operation at a node between the integrated circuit and the source or drain region. Additional apparatus, systems, and methods are disclosed.

Electrostatic Discharge Management Apparatus, Systems, And Methods

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US Patent:
8349676, Jan 8, 2013
Filed:
Aug 19, 2011
Appl. No.:
13/214044
Inventors:
Cong Khieu - San Jose CA, US
Yanjun Ma - Bellvue WA, US
Jaideep Mavoori - Bellevue WA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
H01L 21/337
US Classification:
438193, 257E29255
Abstract:
Apparatus, systems, and methods may include managing electrostatic discharge events by using a semiconductor device having a non-aligned gate to implement a snap-back voltage protection mechanism. Such devices may be formed by doping a semiconductor substrate to form a first conductive region as a well, forming one of a source region and a drain region in the well, depositing a layer of polysilicon on the substrate to establish a gating area that does not overlap the one of the source region and the drain region, and forming an integrated circuit supported by the substrate to couple to the one of the source region and the drain region to provide snap-back voltage operation at a node between the integrated circuit and the source or drain region. Additional apparatus, systems, and methods are disclosed.
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Jaideep Mavoori from Mercer Island, WA, age ~55 Get Report