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Jack F Thomas

from Palo Alto, CA
Age ~79
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Also known as:
Jack E Thomas, Jet F Thomas, John F Thomas
Phone and address:
361 Whitclem Pl, Palo Alto, CA 94306
(408) 616-8629
Related to:
Paul A Thomas, 77Ruth T ThomasJohn W Thomas
Connected to:
Aaisha I Thomas, 39Abby W Thomas, 57Abhay M Thomas, 37Aditya M Thomas, 47Adreanna R Thomas, 33Adrien D Thomas, 50Aerial L Thomas, 40Aileen Thomas, 81Ainsley R Thomas, 82Ajo Thomas, 37

Jack Thomas Phones & Addresses

  • 361 Whitclem Pl, Palo Alto, CA 94306 (408) 616-8629
  • San Lorenzo, CA
  • Sparks, NV

Professional Records

License Records

Jack Russell Thomas

License #:
057068
Category:
CPA (Certified Public Accountant)
Issued Date:
Nov 23, 1987
Type:
CERTIFIED PUBLIC ACCOUNTANCY

Jack W Thomas

License #:
4270 - Expired
Category:
Emergency Medical Care
Issued Date:
Mar 9, 2015
Effective Date:
Jan 5, 2017
Expiration Date:
Dec 31, 2016
Type:
Paramedic

Lawyers & Attorneys

Jack Thomas Photo 1

Jack Thomas - Lawyer

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Specialties:
Criminal Law
Insurance Law
ISLN:
903185507
Admitted:
1982
University:
Ohio University, B.S.C., 1979
Law School:
Ohio State University, J.D., 1982

Medicine Doctors

Jack Thomas Photo 2

Jack G. Thomas

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Specialties:
Family Medicine
Work:
Sanford Health Dickinson Clinic
2615 Fairway St, Dickinson, ND 58601
(701) 456-6000 (phone), (701) 456-6012 (fax)
Education:
Medical School
Oregon Health & Science University School of Medicine
Graduated: 1976
Procedures:
Arthrocentesis
Destruction of Benign/Premalignant Skin Lesions
Electrocardiogram (EKG or ECG)
Skin Tags Removal
Vaccine Administration
Vasectomy
Conditions:
Acute Pharyngitis
Anxiety Phobic Disorders
Diabetes Mellitus (DM)
Hypertension (HTN)
Skin and Subcutaneous Infections
Languages:
English
Spanish
Description:
Dr. Thomas graduated from the Oregon Health & Science University School of Medicine in 1976. He works in Dickinson, ND and specializes in Family Medicine. Dr. Thomas is affiliated with CHI St Josephs Health.
Jack Thomas Photo 3

Jack M. Thomas

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Specialties:
Orthopaedic Surgery
Work:
Greenville Orthopedic
4101 Wesley St STE B, Greenville, TX 75401
(903) 454-7555 (phone), (903) 450-4420 (fax)
Education:
Medical School
University of Texas Medical Branch at Galveston
Graduated: 1975
Procedures:
Carpal Tunnel Decompression
Arthrocentesis
Hip Replacement
Knee Arthroscopy
Knee Replacement
Shoulder Arthroscopy
Shoulder Surgery
Conditions:
Cholelethiasis or Cholecystitis
Fractures, Dislocations, Derangement, and Sprains
Internal Derangement of Knee Cartilage
Intervertebral Disc Degeneration
Osteoarthritis
Languages:
English
Description:
Dr. Thomas graduated from the University of Texas Medical Branch at Galveston in 1975. He works in Greenville, TX and specializes in Orthopaedic Surgery. Dr. Thomas is affiliated with Hunt Regional Medical Center.

Business Records

Name / Title
Company / Classification
Phones & Addresses
Jack Thomas
Manager
Praxair Inc
Industrial Gases
331 E Channel Rd, Benicia, CA 94510
Jack Thomas
Manager
Praxair Inc
Industrial Gases
331 E Channel Rd, Benicia, CA 94510
Jack Thomas
Manager
Praxair Inc
Industrial Gas Manufacturing
331 E Channel Rd, Benicia, CA 94510
(707) 745-5328
Jack H Sr Thomas
Incorporator
The Senior Citizens Center Advisory Board, Tillman's Corner, Alabama
Charitable/religious/educational/scientific Purposes
Jack Thomas
WEB INSURANCE NETWORK, INC
Jack F Thomas
PATHWAY INSURANCE SERVICES, INC
Jack F Thomas
COUPCOUNTS, INC
Jack Holmes Thomas
Incorporator
DIXIE BOWLING LANES, INC
Jack H Thomas
Incorporator
BEEHIVE BUILDING AND LEASING CORPORATION

Publications

Isbn (Books And Publications)

Essays on Socialism

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Author

Jack Ray Thomas

ISBN #

0773499113

Crouching Timmy, Hidden Wanda

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Author

Jack Thomas

ISBN #

0375830642

Head On!

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Author

Jack Thomas

ISBN #

0553233068

Lemonade With a Twist

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Author

Jack Thomas

ISBN #

0689863217

Le Temps Des Foires: Foires Et Marches Dans Le Midi Toulousain De La Fin De L'Ancien Regime a 1914

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Author

Jack Thomas

ISBN #

2858161895

Les Parlements De Province: Pouvoirs, Justice Et Societe Du XVe Au XVIIIe Siecle

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Author

Jack Thomas

ISBN #

2912025001

Jack Ward Thomas: The Journals of a Forest Service Chief

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Author

Jack Ward Thomas

ISBN #

0295983981

Wild Logging: A Guide to Environmentally and Economically Sustainable Forestry

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Author

Jack Ward Thomas

ISBN #

0878424482

Us Patents

Process For Fabricating High Density Memory Cells Using A Metallic Hard Mask

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US Patent:
6399446, Jun 4, 2002
Filed:
Oct 29, 1999
Appl. No.:
09/429722
Inventors:
Bharath Rangarajan - Santa Clara CA
David K. Foote - San Jose CA
Fei Wang - San Jose CA
Dawn M. Hopper - San Jose CA
Stephen K. Park - Austin TX
Jack Thomas - Palo Alto CA
Mark Chang - Los Altos CA
Mark Ramsbey - Sunnyvale CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 218247
US Classification:
438262, 438945
Abstract:
A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is made from tungsten, titanium, or titanium nitride. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then stripped, preferably using an H O solution.

Process For Fabricating High Density Memory Cells Using A Polysilicon Hard Mask

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US Patent:
6436766, Aug 20, 2002
Filed:
Oct 29, 1999
Appl. No.:
09/430493
Inventors:
Bharath Rangarajan - Santa Clara CA
David K. Foote - San Jose CA
Fei Wang - San Jose CA
Dawn M. Hopper - San Jose CA
Stephen K. Park - Austin TX
Jack Thomas - Palo Alto CA
Mark Chang - Los Angeles CA
Mark Ramsbey - Sunnyvale CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 218247
US Classification:
438261, 438262
Abstract:
A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is preferably made from polysilicon or silicon. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then removed, preferably using a plasma etch process.

Integration Of An Ion Implant Hard Mask Structure Into A Process For Fabricating High Density Memory Cells

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US Patent:
6486029, Nov 26, 2002
Filed:
Jul 28, 2000
Appl. No.:
09/627563
Inventors:
David K. Foote - San Jose CA
Bharath Rangarajan - Santa Clara CA
Stephan K. Park - Austin TX
Fei Wang - San Jose CA
Dawn M. Hopper - San Jose CA
Jack Thomas - Palo Alto CA
Mark Chang - Los Altos CA
Mark Ramsbey - Sunnyvale CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 218247
US Classification:
438261, 438954
Abstract:
A process for fabricating a memory cell in a two-bit EEPROM device, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. Preferably, the hard mask includes a material selected from the group consisting of tungsten, titanium, titanium nitride, polysilicon, silicon, silicon nitride, silicon oxi-nitride, and silicon rich nitride. In one preferred embodiment, the process further includes implanting the semiconductor substrate with a p-type dopant at an angle substantially normal to the principal surface of the semiconductor substrate and annealing the semiconductor substrate upon implanting the semiconductor substrate with a p-type dopant. In one preferred embodiment, the process further includes implanting the semiconductor substrate with an n-type dopant.

Self-Aligned Polysilicon Polish

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US Patent:
6610577, Aug 26, 2003
Filed:
May 15, 2002
Appl. No.:
10/150204
Inventors:
Jack F. Thomas - Palo Alto CA
Unsoon Kim - Santa Clara CA
Krishnashree Achuthan - San Ramon CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 218247
US Classification:
438311, 438257, 438258, 438259, 438260, 438261, 438264, 438267, 438296, 438318
Abstract:
A method for removing polysilicon from isolation regions on a substrate during semiconductor fabrication is disclosed. The method includes depositing a layer of polysilicon over the substrate, and depositing at least one dielectric layer over the polysilicon. The method further includes polishing the polysilicon from the isolation regions, wherein the dielectric layers act as a polishing stop, resulting in regions of polysilicon that are self-aligned to the trench isolation regions.

Fully Isolated Dielectric Memory Cell Structure For A Dual Bit Nitride Storage Device And Process For Making Same

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US Patent:
6639271, Oct 28, 2003
Filed:
Dec 20, 2001
Appl. No.:
10/027253
Inventors:
Wei Zheng - Sunnyvale CA
Mark W. Randolph - San Jose CA
Nicholas H. Tripsas - San Jose CA
Zoran Krivokapic - Santa Clara CA
Jack F. Thomas - Palo Alto CA
Mark T. Ramsbey - Sunnyvale CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 29792
US Classification:
257324, 257329, 257314, 257327, 438212
Abstract:
A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.

Shallow Trench Isolation Fill Process

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US Patent:
6670691, Dec 30, 2003
Filed:
Jun 18, 2002
Appl. No.:
10/174550
Inventors:
Harpreet K. Sachar - Pleasanton CA
Unsoon Kim - Santa Clara CA
Jack F. Thomas - Palo Alto CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 2900
US Classification:
257510, 257 50, 257499, 257514, 438410, 438424, 438445
Abstract:
A method for filling narrow isolation trenches during a semiconductor fabrication process is disclosed. The semiconductor includes both high-aspect ratio narrow isolation trenches formed in a core area of a substrate, and wide isolation trenches formed in a circuit area of the substrate. After trench formation, a thick liner oxidation is performed in all of the isolation trenches in which a layer of thermal oxide is grown to a thickness sufficient to completely fill the high-aspect ratio narrow isolation trenches. Subsequent to the liner oxidation, the wide isolation trenches are filled with an isolation dielectric, whereby all of the trenches are uniformly filled with minimal voids.

Fully Isolated Dielectric Memory Cell Structure For A Dual Bit Nitride Storage Device And Process For Making Same

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US Patent:
6861307, Mar 1, 2005
Filed:
Jul 31, 2003
Appl. No.:
10/631199
Inventors:
Wei Zheng - Sunnyvale CA, US
Mark W. Randolph - San Jose CA, US
Nicholas H. Tripsas - San Jose CA, US
Zoran Krivokapic - Santa Clara CA, US
Jack F. Thomas - Palo Alto CA, US
Mark T. Ramsbey - Sunnyvale CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L021/8238
US Classification:
438216, 438212
Abstract:
A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.

Fully Isolated Dielectric Memory Cell Structure For A Dual Bit Nitride Storage Device And Process For Making Same

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US Patent:
7001807, Feb 21, 2006
Filed:
Nov 24, 2004
Appl. No.:
10/997345
Inventors:
Wei Zheng - Sunnyvale CA, US
Mark W. Randolph - San Jose CA, US
Nicholas H. Tripsas - San Jose CA, US
Zoran Krivokapic - Santa Clara CA, US
Jack F. Thomas - Palo Alto CA, US
Mark T. Ramsbey - Sunnyvale CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 21/31
US Classification:
438216, 438267
Abstract:
A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.
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Jack F Thomas from Palo Alto, CA, age ~79 Get Report