Jack G Regula

6400682, Jun 4, 2002

Feb 16, 1999

09/251135

Jack Regula - San Jose CA

PLX Technology, Inc. - Sunnyvale CA

G01R 3108

370223, 370258

The disclosure relates to apparatus and methods that provide a system interconnect for transporting cells between nodes on a dual counter-rotating ring network, including a link selection register for selecting the shortest path to a destination node, use of a fault tolerant frequency reference to synchronize node clocks, interconnect initialization, multi-ring topologies along with an addressing schema and ring-to-ring couplers. The disclosure also discusses flow control of cells leaving nodes, coupling cells from one ring to another, and use of such an interconnect as a bus replacement.

6581126, Jun 17, 2003

May 19, 1999

09/315412

Jack Regula - San Jose CA

PLX Technology, Inc. - Sunnyvale CA

G06F 1328

710305, 710 31, 370351, 370392, 709239, 709242

The invention discloses methods and apparatus for broadcasting information across an interconnect that includes a plurality of nodes each connected to its adjacent node(s) using one or more links. The nodes can emit cells containing transaction sub-actions onto the links. As a node receives a cell the node retransmits the cell onto other links as the cell is being received. Thus, reducing the latency imposed by the node. The node also captures the transaction sub-action while it the cell is retransmitted. The node responds to the transaction sub-action by manipulating shared handshake lines that are bussed with the other nodes. The invention enables snooping cache protocols to be successfully used in a larger multi-processor computer system than the prior art.

6851009, Feb 1, 2005

May 28, 2003

10/446402

Jack Regula - San Jose CA, US

PLX Technology, Inc. - Sunnyvale CA

G06F 1314
H04L 1228

710305, 710 31, 370392, 711141

The invention discloses methods and apparatus for broadcasting information across an interconnect that includes a plurality of nodes each connected to its adjacent node(s) using one or more links. The nodes can emit cells containing transaction sub-actions onto the links. As a node receives a cell the node retransmits the cell onto other links as the cell is being received. Thus, reducing the latency imposed by the node. The node also captures the transaction sub-action while it the cell is retransmitted. The node responds to the transaction sub-action by manipulating shared handshake lines that are bussed with the other nodes. The invention enables snooping cache protocols to be successfully used in a larger multi-processor computer system than the prior art.

6885670, Apr 26, 2005

Oct 19, 1999

09/421771

Jack Regula - San Jose CA, US

PLX Technology, Inc. - Sunnyvale CA

H04L012/28

370401, 370254, 370402

The disclosure relates to apparatus and methods that provide a system interconnect for transporting cells between nodes on a dual counter-rotating ring network, including a link selection register for selecting the shortest path to a destination node, use of a fault tolerant frequency reference to synchronize node clocks, interconnect initialization, multi-ring topologies along with an addressing schema and ring-to-ring couplers. The disclosure also discusses flow control of cells leaving nodes, coupling cells from one ring to another, and use of such an interconnect as a bus replacement.

7039750, May 2, 2006

Jul 24, 2001

09/912231

Jack Regula - San Jose CA, US
Jhy-Ping Shaw - San Jose CA, US
Ronald A. Simmons - Bountiful UT, US
Curtis Winward - Lehi UT, US
Ralph Woodard - Mountain View CA, US
William Wu - Cupertino CA, US

PLX Technology, Inc. - Sunnyvale CA

G06F 13/00

710317, 710242

A system for communication on a chip. The system includes an on-chip communication bus including plural tracks, and a plurality of stations that couple a plurality of on-chip components to the on-chip communication bus, whereby the plurality of on-chip components use the tracks to communicate. Each station preferably includes an initiator that requests permission to transmit outgoing data over a track to another station and that transmits the outgoing data, an arbiter that evaluates requests from other stations and selects a track on which to receive incoming data, and a target that receives the incoming data. The initiator can be connected to a grant multiplexor for selecting a grant line, with the grant multiplexor further including plural smaller multiplexors distributed across the chip. Likewise, the arbiter can be connected to a track multiplexor for selecting a track, with the track multiplexor further including plural smaller multiplexors distributed across the chip. Each station also can include a source queue for queuing outgoing data and a destination queue for queuing incoming data.

8521941, Aug 27, 2013

Dec 28, 2010

12/979904

Jack Regula - Chapel Hill NC, US

PLX Technology, Inc. - Sunnyvale CA

G06F 13/42
G06F 13/20

710313, 710105, 710305

In a first embodiment of the present invention, a method for multi-root sharing of a plurality of single root input/output virtualization (SR-IOV) endpoints is provided, the method comprising: CSR redirection to a management processor which either acts as a proxy to execute the CSR request on behalf of the host or filters it and performs an alternate action, downstream routing of memory mapped I/O request packets through the switch in the host's address space and address translation with VF BAR granularity, upstream routing of requests originated by I/O devices by table lookup indexed by Requester ID, and requester ID translation using a fixed local-global RID offset.

8553683, Oct 8, 2013

Jul 5, 2011

13/176350

Jack Regula - Chapel Hill NC, US

PLX Technology, Inc. - Sunnyvale CA

H04L 12/00

370388, 370387, 370230

In a first embodiment of the present invention, a non-blocking switch fabric is provided comprising: a first set of intra-domain switches; a second set of intra-domain switches; a set of inter-domain switches located centrally between the first set of intra-domain switches and the second set of intra-domain switches, wherein each of the ports of each of the inter-domain switches is connected to an intra-domain switch from the first or second set of intra-domain switches.

8645605, Feb 4, 2014

Aug 18, 2011

13/212700

Nagarajan Subramaniyan - San Jose CA, US
Jack Regula - Chapel Hill NC, US
Jeffrey Michael Dodson - Portland OR, US

PLX Technology, Inc. - Sunnyvale CA

G06F 13/20

710313, 710305, 710104, 719321

A method is provided comprising: enumerating a group of available virtual functions corresponding to the physical function; mapping the group of available virtual functions to a non-transparent port of the switch by creating a copy of a configuration space for the physical function while assigning unique vendor and device identifications for different classes of devices, wherein the mapping creates a pseudo physical function exposing a subset of the SR-IOV capability from the configuration space for the physical function; receiving a request to access the physical function from the single host; and providing the pseudo physical function to the single host for loading on the single host, in response to the receiving of the request, wherein the pseudo physical function is designed to call management functions of the single host to enable the group of available virtual functions in a local hierarchy of the single host.