Ivor G Barber

6590292, Jul 8, 2003

Jun 1, 2001

09/872327

Ivor G. Barber - Los Gatos CA
Zafer S. Kutlu - Menlo Park CA

LSI Logic Corporation - Milpitas CA

H01L 2348

257778, 257704, 257783

An integrated circuit structure and a method for packaging an integrated circuit are described. The integrated structure includes an integrated circuit that is inverted and solder bump mounted to a substrate. An underfill is used to encapsulate the solder bumps and form a rigid support layer between the integrated circuit and the substrate. A heatspreader, which has larger planar dimensions than the integrated circuit, is centrally attached to an upper surface of the integrated circuit with a thermally conductive material. Lateral portions of the heatspreader extending beyond the edges of the integrated circuit are attached to the substrate and sides of the integrated circuit by a thermally conductive underfill material. The thermally conductive underfill material thus employed, among other things, provides a robust mechanical support to the heatspreader and integrated circuit structure and eliminates the need for additional support structures such as conventional stiffener rings.

6673708, Jan 6, 2004

Mar 25, 2003

10/397065

Ivor G. Barber - Los Gatos CA
Zafer S. Kutlu - Menlo Park CA

LSI Logic Corporation - Milpitas CA

H01L 2144

438608, 438122

An integrated circuit structure and a method for packaging an integrated circuit are described. The integrated structure includes an integrated circuit that is inverted and solder bump mounted to a substrate. An underfill is used to encapsulate the solder bumps and form a rigid support layer between the integrated circuit and the substrate. A heatspreader, which has larger planar dimensions than the integrated circuit, is centrally attached to an upper surface of the integrated circuit with a thermally conductive material. Lateral portions of the heatspreader extending beyond the edges of the integrated circuit are attached to the substrate and sides of the integrated circuit by a thermally conductive underfill material. The thermally conductive underfill material thus employed, among other things, provides a robust mechanical support to the heatspreader and integrated circuit structure and eliminates the need for additional support structures such as conventional stiffener rings.

6943446, Sep 13, 2005

Nov 8, 2002

10/290953

John P. McCormick - Palo Alto CA, US
Ivor G. Barber - Los Gatos CA, US
Kumar Nagarajan - San Jose CA, US

LSI Logic Corporation - Milpitas CA

H01L023/34
H01L023/48
H01L023/52

257728, 257774, 257773, 257737, 257738, 257734, 257778, 257724, 257725, 257691, 257698, 257207, 257208, 257211

An integrated circuit having electrically conductive vias with a diameter of between about one micron and about fifty microns. Prior art vias have a diameter of between no less than 0. 3 microns to no more than 0. 8 microns. In this manner, stresses such as those that press down upon the top surface of the integrated circuit can be absorbed by the large vias and transferred past fragile layers, such as low k layers, so that the fragile layers are not damaged by the stresses.

7173328, Feb 6, 2007

Apr 6, 2004

10/819684

Ivor Barber - Los Gatos CA, US

LSI Logic Corporation - Milpitas CA

H01L 23/48

257694, 257723, 257688, 438107, 438117

A semiconductor package having a substrate mounted die. The die configured having active circuit components and a top surface having bond pads electrically connected with circuitry of the die. The bond pads commonly being formed above active circuit components. The bond pads being electrically interconnected with wire bonds to establish intra-chip electrical connection between circuitry of the die. Methods of forming such packages are also disclosed.

7508062, Mar 24, 2009

Mar 11, 2005

11/078052

Leah Miller - Fremont CA, US
Ivor Barber - Los Gatos CA, US
Aritharan Thurairajaratnam - San Jose CA, US

LSI Corporation - Milpitas CA

H01L 23/053
H01L 23/12

257700, 257E23175, 257532, 257698, 174260, 174262, 333 22 R

The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.

7829424, Nov 9, 2010

Jul 16, 2008

12/174479

Leah Miller - Fremont CA, US
Ivor Barber - Los Gatos CA, US
Aritharan Thurairajaratnam - San Jose CA, US

LSI Corporation - Milpitas CA

H01L 21/20

438379, 361780, 257700

The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.

20090285261, Nov 19, 2009

May 17, 2008

12/122682

Michael J. Casey - East Twickenham, GB
Ivor G. Barber - Los Gatos CA, US
Gregory S. Winn - Ft. Collins CO, US
Julie L. Beatty - Campbell CA, US
Daniel G. Deisz - McLean VA, US

LSI CORPORATION - Milpitas CA

G01K 7/16
G01K 1/00
G01K 7/00

374178, 374100, 374163, 374E07001, 374E07018

A temperature monitoring circuit for an integrated circuit on a monolithic chip, the temperature monitoring circuit comprising a temperature sensor disposed on the monolithic chip, a system monitor disposed on the monolithic chip, and electrically conductive traces for electrically connecting the temperature sensor to the system monitor. In this manner, the temperature on the monolithic chip can be monitored by the integrated circuit itself, and appropriate action can be programmed to occur upon attaining various set points or conditions.

58959688, Apr 20, 1999

Oct 24, 1997

8/957519

Ivor Barber - San Jose CA

H01L 2348

257692

A semiconductor device assembly having external connections, including power supply connections such as to a power source or ground, is made without resort to bond fingers. Rather, external connections are directly made from a semiconductor die to a conductive layer. The conductive layer is disposed on one surface of a printed wring board and is divided into electrically insulated conductive segments. Each of the conductive segments is connected to an external connection, and includes one or more interconnects that can be directly connected to a semiconductor die. The conductive segments are surrounded by an array of bond fingers which serve to connect the semiconductor die to further external connections, such as signal connections. The present invention is especially advantageous in the fabrication of pin grid array (PGA) and ball grid array (BGA) type integrated circuit packages.