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Indradeep T Ghosh

from Cupertino, CA
Age ~54
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Also known as:
Indra Deep Ghosh, D Chosh, P Ghosh
Phone and address:
18870 Barnhart Ave, Cupertino, CA 95014
Related to:
Arpita Ghosh, 46
Connected to:
Adhir K Ghosh, 77Alak Ghosh, 54Aloke N Ghosh, 69Amber N Ghosh, 51Amit GhoshAmlan Ghosh, 43Anamitra Ghosh, 44Angel Ghosh, 34Ankita R Ghosh, 34Anton T Ghosh, 46

Indradeep Ghosh Phones & Addresses

  • 18870 Barnhart Ave, Cupertino, CA 95014
  • Sunnyvale, CA
  • 1672 Lederer Cir, San Jose, CA 95131 (408) 452-1892
  • Princeton, NJ
  • La Jolla, CA
  • Santa Clara, CA

Work

Company: Fujitsu Oct 2018 Position: Senior director of research

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Princeton University 1993 to 1998 Specialities: Electronics, Computer Engineering, Engineering, Communications, Philosophy

Skills

Java • Software Development • Linux • Algorithms • Distributed Systems • Software Engineering • C++ • Python • Perl • Sql • C • Machine Learning • Cloud Computing • System Architecture • Computer Science

Languages

English • Bengali • Hindi

Interests

Miljö • Validation and Verification • Boating • Christianity • Electronics • Outdoors • Reading • Clean Energy and Sustainable Living • Crafts • Sports • Family Values • Collecting • Software Testing

Industries

Computer Software

Resumes

Resumes

Indradeep Ghosh Photo 1

Senior Director Of Research

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Location:
18870 Barnhart Ave, Cupertino, CA 95014
Industry:
Computer Software
Work:
Fujitsu
Senior Director of Research
Fujitsu Jul 2014 - Sep 2018
Director of Research
Santa Clara University Jul 2014 - Sep 2018
Adjunct Faculty
Fujitsu Oct 2010 - Jun 2014
Research Manager
Fujitsu May 1998 - Sep 2010
Member of Research Staff
Education:
Princeton University 1993 - 1998
Doctorates, Doctor of Philosophy, Electronics, Computer Engineering, Engineering, Communications, Philosophy Indian Institute of Technology, Kharagpur 1989 - 1993
Bachelors, Bachelor of Technology, Computer Science, Engineering St. Mary's Orphanage and Day School, Dum Dum, Kolkata
Calcutta Boys School
Skills:
Java
Software Development
Linux
Algorithms
Distributed Systems
Software Engineering
C++
Python
Perl
Sql
C
Machine Learning
Cloud Computing
System Architecture
Computer Science
Interests:
Miljö
Validation and Verification
Boating
Christianity
Electronics
Outdoors
Reading
Clean Energy and Sustainable Living
Crafts
Sports
Family Values
Collecting
Software Testing
Languages:
English
Bengali
Hindi

Publications

Isbn (Books And Publications)

Verification Techniques for System-Level Design

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Author

Indradeep Ghosh

ISBN #

0123706165

Us Patents

Automatic Test Pattern Generation For Functional Register Transfer Level Circuits Using Assignment Decision Diagrams

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US Patent:
6823486, Nov 23, 2004
Filed:
May 8, 2001
Appl. No.:
09/851708
Inventors:
Indradeep Ghosh - San Jose CA
Assignee:
Fujitsu Limited - Kawasaki
International Classification:
G01R 313183
US Classification:
714738
Abstract:
Test patterns are generated by generating assignment decision diagrams that represent a register transfer level digital circuit. A nine-valued symbolic algebra is used in which objectives are determined for portions identified in the assignment decision diagram. The objectives are justified and propagated by traversing the assignment decision diagram in which a test environment is found. Heuristics are used if a test environment is not initially found. Using the test environment found, predetermined test vectors are propagated to obtain a system-level test set. Each test set for each portion are concatenated to obtain a complete test set for the register transfer level digital circuit.

Evaluating A Validation Vector For Validating A Network Design

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US Patent:
6877141, Apr 5, 2005
Filed:
Apr 1, 2003
Appl. No.:
10/405767
Inventors:
Indradeep Ghosh - San Jose CA, US
Koichiro Takayama - Cupertino CA, US
Liang Zhang - Blacksburg VA, US
Assignee:
Fujitsu Limited - Kawasaki
International Classification:
G06F017/50
US Classification:
716 4, 716 5, 716 18
Abstract:
Evaluating a validation vector includes receiving a network having nodes and a target set that includes one or more nodes of the network. The following steps are repeated until the nodes of the target set have been selected. A node is selected from the target set, and a tag is assigned to the node, where the tag represents an error of a value of a variable corresponding to the node. A test environment specifying a propagation path from an input, through the node, and to an output is generated. The test environment is translated into a validation vector, and the tag is propagated to the output according to the validation vector. After repeating the steps, coverage for the validation vectors is determined in accordance with the propagation to evaluate the one or more validation vectors.

Generating A Test Environment For Validating A Network Design

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US Patent:
7139929, Nov 21, 2006
Filed:
Apr 1, 2003
Appl. No.:
10/405768
Inventors:
Indradeep Ghosh - San Jose CA, US
Liang Zhang - Blacksburg VA, US
Assignee:
Fujitsu Limited - Kawasaki
International Classification:
G06F 11/00
US Classification:
714 4
Abstract:
Generating a test environment includes accessing initial test environments for a network of nodes, where a test environment specifies a propagation or justification path for a node. The following are repeated until satisfactory coverage is achieved or until a predetermined number of iterations is reached. A coverage for each test environment is calculated, and at least two of the test environments are mated to generate next test environments, where the coverage of the at least two test environments is greater than the coverage of the other test environments.

Propagating An Error Through A Network

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US Patent:
7168014, Jan 23, 2007
Filed:
Apr 1, 2003
Appl. No.:
10/405766
Inventors:
Indradeep Ghosh - San Jose CA, US
Koichiro Takayama - Cupertino CA, US
Liang Zhang - Blacksburg VA, US
Assignee:
Fujitsu Limited - Kawasaki
International Classification:
G01R 31/28
US Classification:
714712, 716 4
Abstract:
Propagating an error through a network includes receiving a network having propagation paths and nodes, where a propagation path has one or more nodes and a node is associated with a variable operable to have a value during simulation. A tag of a tag set is assigned to the value. The tag set includes at least two signed tags, positive tag representing a positive error and a negative tag representing a negative error, and an unsigned tag representing an error having an unknown sign. The tag is propagated along the propagation path to yield intermediate tags, where at least one intermediate tag is an unsigned tag formed from at least two signed tags. A final tag is determined in accordance with the intermediate tags in order to propagate an error through the network.

Event-Driven Observability Enhanced Coverage Analysis

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US Patent:
7210128, Apr 24, 2007
Filed:
Oct 14, 2002
Appl. No.:
10/270835
Inventors:
Farzan Fallah - San Jose CA, US
Indradeep Ghosh - San Jose CA, US
Assignee:
Fujitsu Limited - Kawasaki
International Classification:
G06F 9/44
G06F 9/45
G06F 17/00
G06F 7/00
US Classification:
717135, 717124, 717143, 717154, 707102, 7071041
Abstract:
A method for event-driven observability enhanced coverage analysis of a program parses a program into variables and data dependencies, wherein the data dependencies comprise assignments and operations. The method builds a data structure having multiple records, with each record having at least one data dependency, a parent node, and a child node. Each node is linked to a variable. The method computes the value of each variable using the data structure. The method performs tag propagation based, at least in part, on the data dependencies and computed values.

Estimating The Difficulty Level Of A Formal Verification Problem

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US Patent:
7458046, Nov 25, 2008
Filed:
Jul 19, 2005
Appl. No.:
11/185231
Inventors:
Indradeep Ghosh - San Jose CA, US
Mukul R. Prasad - Sunnyvale CA, US
Assignee:
Fujitsu Limited - Kawasaki
International Classification:
G06F 17/50
US Classification:
716 5, 716 4, 716 6, 714738
Abstract:
Estimating the difficulty level of a verification problem includes receiving input comprising a design and properties that may be verified on the design. Verification processes are performed for each property on the design. A property verifiability metric value is established for each property in accordance with the verification processes, where a property verifiability metric value represents a difficulty level of verifying the property on the design. A design verifiability metric value is determined from the property verifiability metric values, where the design verifiability metric value represents a difficulty level of verifying the design.

System And Method For Detecting Software Defects

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US Patent:
7685471, Mar 23, 2010
Filed:
Feb 1, 2007
Appl. No.:
11/670143
Inventors:
Sreeranga P. Rajan - Sunnyvale CA, US
Oksana Tkachuk - Palo Alto CA, US
Mukul R. Prasad - San Jose CA, US
Indradeep Ghosh - San Jose CA, US
Assignee:
Fujitsu Limited - Kawasaki
International Classification:
G06F 11/00
US Classification:
714 38, 717124, 717126
Abstract:
A method for detecting software defects includes selecting from a target program comprising a plurality of modules a first module for evaluation and isolating the first module. The method also includes iteratively performing the following steps until the first module has been reduced such that a validation program is able to determine whether the first module contains a defect: generating an environment surrounding the first module, the generated environment preserving at least one external constraint on the first module; reducing the size of the first module; and reducing the number of program states associated with the first module.

System And Method For Providing Middleware For Capture Of Global Requirements And Validation For Web Applications

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US Patent:
8271953, Sep 18, 2012
Filed:
Mar 12, 2008
Appl. No.:
12/046736
Inventors:
Mukul R. Prasad - San Jose CA, US
Indradeep Ghosh - San Jose CA, US
Sreeranga P. Rajan - Sunnyvale CA, US
Assignee:
Fujitsu Limited - Kawasaki
International Classification:
G06F 9/44
US Classification:
717126, 717124, 717131
Abstract:
In accordance with a particular embodiment of the present invention, a method is offered that includes supporting requirement validation middleware and capturing global requirements or properties for one or more web applications. A template-based formalism is employed to capture the requirements or properties. A small set of relevant temporal patterns are provided from which to choose in capturing the global requirements or properties. In specific embodiments, the method uses a set of pre-coded semi-configurable checkers. A Java-like syntax is used to specify expressions. A library of atomic entities or events (to compose expressions) is automatically generated. In still other embodiments, a small set of light-weight automatically-customizable checkers are employed in capturing the global requirements or properties. The method can be used with both formal and semi-formal techniques.
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Indradeep T Ghosh from Cupertino, CA, age ~54 Get Report