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Ilie X Garbacea

from Santa Clara, CA
Age ~64
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Also known as:
Ilie Garbecea, Ilie Gardace, Ilie A
Phone and address:
3213 Colgate Ave, Santa Clara, CA
(408) 296-4119
Related to:
Delia M Garbacea, 63
Connected to:
Anna Garbaciak, 102Roy M Garbacik, 70Alicja Garbacz, 73Ginger N Garbacz, 72Janine K Garbacz, 57Walter W Garbacz, 71Wojciech J Garbacz, 52Rashid S Garbadawala, 50Jorge J Garbalosa, 44Charlene J Garban, 71

Ilie Garbacea Phones & Addresses

  • 3213 Colgate Ave, Santa Clara, CA (408) 296-4119
  • Sunnyvale, CA
  • 3213 Colgate Ave, Santa Clara, CA 95051

Work

Company: Apple 2014 Position: Engineer

Education

Degree: Master of Science, Doctorates, Masters, Doctor of Philosophy School / High School: „Babeș - Bolyai” University, Cluj - Napoca Romania 1990 to 1996 Specialities: Mathematics, Computer Science

Skills

Computer Architecture and Compilers • Embedded Systems • Video Analytics Cpu/Gpu Processing • Communication and Synchronization In Mul... • Languages and Libraries For Parallel Pro... • Hardware Software Co Design and Modeling

Industries

Consumer Electronics

Resumes

Resumes

Ilie Garbacea Photo 1

Engineer

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Location:
Santa Clara, CA
Industry:
Consumer Electronics
Work:
Apple
Engineer
Mips Sunnyvale Ca 2006 - 2014
Staff Architect
Mobilygen Santa Clara Ca 2000 - 2006
Chief Software Architect
Zoran Santa Clara Ca 1995 - 2000
Chief Architect and Lead Developer
Education:
„Babeș - Bolyai” University, Cluj - Napoca Romania 1990 - 1996
Master of Science, Doctorates, Masters, Doctor of Philosophy, Mathematics, Computer Science
Skills:
Computer Architecture and Compilers
Embedded Systems
Video Analytics Cpu/Gpu Processing
Communication and Synchronization In Multi Core Systems
Languages and Libraries For Parallel Programming
Hardware Software Co Design and Modeling

Publications

Us Patents

Matrix Of Processors With Data Stream Instruction Execution Pipeline Coupled To Data Switch Linking To Neighbor Units By Non-Contentious Command Channel / Data Channel

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US Patent:
7870365, Jan 11, 2011
Filed:
Jul 7, 2008
Appl. No.:
12/168857
Inventors:
Sorin C Cismas - Saratoga CA, US
Ilie Garbacea - Santa Clara CA, US
Assignee:
Ovics - Saratoga CA
International Classification:
G06F 15/17
US Classification:
712 16, 710316, 712225
Abstract:
In some embodiments, control and data messages are transmitted non-contentiously over corresponding control and data channels of inter-processor links in a matrix of mesh-interconnected matrix processors. A data stream instruction executed by a user thread of an instruction processing pipeline of a matrix processor may initiate a data stream transfer by a hardware data switch of the matrix processor over multiple consecutive cycles over a data channel. While the data stream is being transferred, the corresponding control channel may transfer control messages non-contentiously with respect to the data stream. The control messages may be messages received from other matrix processors and/or control messages initiated by a kernel thread of the current matrix processor.

Processing Stream Instruction In Ic Of Mesh Connected Matrix Of Processors Containing Pipeline Coupled Switch Transferring Messages Over Consecutive Cycles From One Link To Another Link Or Memory

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US Patent:
7958341, Jun 7, 2011
Filed:
Jul 7, 2008
Appl. No.:
12/168861
Inventors:
Sorin C Cismas - Saratoga CA, US
Ilie Garbacea - Santa Clara CA, US
Assignee:
Ovics - Saratoga CA
International Classification:
G06F 13/14
US Classification:
712225, 710316, 712 10
Abstract:
In some embodiments, each matrix processor in a matrix of mesh-interconnected matrix processors includes an instruction processing pipeline, and a hardware data switch capable of streaming data to/from one or more inter-processor matrix links and/or a matrix processor local memory links in response to execution of a data streaming instruction by the instruction processing pipeline. The data switch can transfer each data stream, which includes multiple words, at wire speed, one word per cycle. After initiating a data stream, the processing pipeline can execute other instructions, including streaming instructions, while a stream transfer is in progress. Different data streaming instructions may be used to transfer data streams from local memory to one or more inter-processor links, from an inter-processor link to local memory, from an inter-processor link to one or more inter-processor links, and from an inter-processor link to one or more inter-processor links and synchronously to local memory.

Method And Apparatus Of Adaptive Lambda Estimation In Lagrangian Rate-Distortion Optimization For Video Coding

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US Patent:
8094716, Jan 10, 2012
Filed:
Nov 8, 2005
Appl. No.:
11/268803
Inventors:
Lulin Chen - Cupertino CA, US
Ilie Garbacea - Santa Clara CA, US
Assignee:
Maxim Integrated Products, Inc. - Sunnyvale CA
International Classification:
H04N 7/12
US Classification:
37524003, 37524001, 37524016, 37524018
Abstract:
A method for hybrid video coding is disclosed. The method generally includes the steps of (A) calculating a bit rate based on a percentage of quantized zero coefficients resulting from encoding a plurality of components of a video signal, (B) calculating a distortion based on the percentage of quantized zero coefficients, (C) calculating a plurality of variances of a plurality of prediction error pictures and (D) calculating an adaptive Lagrangian multiplier in a Lagrangian rate-distortion optimization as a function of the bit rate, the distortion and the variance to minimize a Lagrangian cost.

Video Encoding Statistics Extraction Using Non-Exclusive Content Categories

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US Patent:
8126283, Feb 28, 2012
Filed:
Oct 13, 2005
Appl. No.:
11/250102
Inventors:
Ilie Garbacea - Santa Clara CA, US
Lulin Chen - Cupertino CA, US
Jose R. Alvarez - Sunnyvale CA, US
Assignee:
Maxim Integrated Products, Inc. - Sunnyvale CA
International Classification:
G06K 9/46
US Classification:
382243, 382232, 382239, 375240, 37524002, 37524008, 37524024
Abstract:
In some embodiments, content-category-level encoding statistical indicators (statistics) are assigned to weighted linear combinations of corresponding macroblock-level statistics. Content categories may identify potentially overlapping content types such as sky, water, grass, skin, and red content. The combination weights may be similarity measures describing macroblock similarities to content categories. A given macroblock may be associated with multiple content categories, with different similarity levels for different content categories. A similarity measure for a given macroblock with respect to a content category may be defined as a number (between 0 and 8) of neighboring macroblocks that meet a similarity condition, provided the macroblock meets a qualification condition. The similarity condition may be computationally simpler than the qualification condition. Macroblock-level encoding parameters are generated by combining content-category-level parameters.

Matrix Processor Initialization Systems And Methods

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US Patent:
8131975, Mar 6, 2012
Filed:
Jul 7, 2008
Appl. No.:
12/168837
Inventors:
Sorin C Cismas - Saratoga CA, US
Ilie Garbacea - Santa Clara CA, US
Assignee:
Ovics - Saratoga CA
International Classification:
G06F 15/76
US Classification:
712 11, 712 16
Abstract:
In some embodiments, an integrated circuit comprises a microprocessor matrix including a plurality of mesh-interconnected matrix processors, wherein each matrix processor comprises a data switch configured to direct inter-processor communications within the matrix, and a mapping unit configured to generate a data switch functionality map for a plurality of data switches in the microprocessor matrix. The data switch functionality map is generated by sending a first message through the matrix, and, setting a first functionality status designation for the first data switch in the data switch functionality map upon receiving a reply to the first message from a first data switch through the matrix.

Matrix Processor Data Switch Routing Systems And Methods

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US Patent:
8145880, Mar 27, 2012
Filed:
Jul 7, 2008
Appl. No.:
12/168853
Inventors:
Sorin C Cismas - Saratoga CA, US
Ilie Garbacea - Santa Clara CA, US
Assignee:
Ovics - Saratoga CA
International Classification:
G06F 15/76
US Classification:
712 11, 712 16
Abstract:
According to some embodiments, an integrated circuit comprises a microprocessor matrix of mesh-interconnected matrix processors. Each processor comprises a data switch including a data switch link register and matrix routing logic. The data switch link register includes one or more matrix link-enable register fields specifying a link enable status (e. g. a message-independent, p-to-p, and/or broadcast link enable status) for each inter-processor matrix link of the processor. The matrix routing logic routes inter-processor messages according to the matrix link-enable register field(s). A particular link may be selected by a current matrix processor by selecting an ordered list of matrix links according to a relationship between ΔH and ΔV, and choosing the first enabled link in the selected list for routing. ΔH is the horizontal matrix position difference between the current (sender) processor and a destination processor, and ΔV is the vertical matrix position difference between the current and destination processors.

Video Encoding Control Using Non-Exclusive Content Categories

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US Patent:
8149909, Apr 3, 2012
Filed:
Oct 13, 2005
Appl. No.:
11/249213
Inventors:
Ilie Garbacea - Santa Clara CA, US
Lulin Chen - Cupertino CA, US
Jose R. Alvarez - Sunnyvale CA, US
Assignee:
Maxim Integrated Products, Inc. - Sunnyvale CA
International Classification:
H04N 7/12
H04N 11/04
US Classification:
37524003, 3484031
Abstract:
In some embodiments, macroblock-level encoding parameters are assigned to weighted Linear combinations of corresponding content-category-level encoding parameters. A macroblock quantization parameter (QP) modulation is set to a weighted linear combination of content category QP modulations. Content categories may identify potentially overlapping content types. The combination weights may be similarity measures describing macroblock similarities to content categories. A macroblock may be associated with multiple content categories, with different similarity levels for different content categories. A similarity measure for a given macroblock with respect to a content category may be defined as a number (between 0 and 8) of neighboring macroblocks that meet a similarity condition, provided the macroblock meets a qualification condition. The similarity condition may be computationally simpler than the qualification condition. Content-category-level statistics are generated by combining block-level statistics.

Matrix Processor Proxy Systems And Methods

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US Patent:
8327114, Dec 4, 2012
Filed:
Jul 7, 2008
Appl. No.:
12/168849
Inventors:
Sorin C Cismas - Saratoga CA, US
Ilie Garbacea - Santa Clara CA, US
Assignee:
Ovics - Saratoga CA
International Classification:
G06F 15/76
US Classification:
712 16, 712 11
Abstract:
In some embodiments, processor-to-processor and/or broadcast proxies are designated in a microprocessor matrix comprising a plurality of mesh-interconnected matrix processors when default processor-to-processor or broadcast routing algorithms used by data switches within the matrix to route messages would not deliver the messages to all intended recipients. The broadcast proxies broadcast messages within individual non-overlapping broadcast domains of the matrix. P-to-P and broadcast proxies may be designated as part of a boot-time testing/initialization sequence. Improving system fault tolerance allows improving semiconductor processing yields, which may be of particular significance in relatively large integrated circuits including large numbers of relatively-complex matrix processors.
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Ilie X Garbacea from Santa Clara, CA, age ~64 Get Report