Ikuo Jimmy Sanwo

6472906, Oct 29, 2002

Dec 27, 2000

09/749704

Ikuo Jimmy Sanwo - San Marcos CA
Mahyar Nejat - San Diego CA
Jean-Robert Clerge - Escondido CA

Sony Corporation - Tokyo
Sony Electronics Inc. - Park Ridge NJ

H03K 190175

326 83, 326 27, 326 81

An open drain I/O driver includes an input node, an output node, a first reference node, a first transistor, and noise immunity circuitry. The first transistor has its gate coupled to the input node and its conducting path coupled in series with the output node and the first reference node. The first transistor operates to uncouple the output node from the first reference node in response to an input voltage applied to the input node. The noise immunity circuitry keeps the output node uncoupled from the first reference node during undershoot noise in a first reference voltage that causes the first transistor to change from an off state to an on state. The noise immunity circuitry includes second and third transistors. The second transistor has its gate coupled to the input node and its conducting path coupled in series with the conducting path of the first transistor. The third transistor is configured to keep the second transistor in an off state during the undershoot noise.

20020089354, Jul 11, 2002

Jan 8, 2001

09/755854

Ikuo Sanwo - San Marcos CA, US
Mahyar Nejat - San Diego CA, US
Jean-Robert Clerge - Phoenix AZ, US

H03K019/094

326/121000

The present invention is a method and apparatus for providing a four input logic function. The apparatus comprises: a coupling circuit; a first circuit having at least a first input terminal for receiving a first input signal and a second input terminal for receiving a second input signal wherein the first circuit uses the coupling circuit for coupling the first and second input signals so as to generate an output signal wherein the output signal being a logic relationship between the first and second input signals; a second circuit having at least a third input terminal for receiving a third input signal and a fourth input terminal for receiving a fourth input signal wherein the second circuit uses the coupling circuit for coupling the third and fourth input signals so as to generate an output signal wherein the output signal being a logic relationship between the third and fourth input signals; and a third circuit using the coupling circuit for coupling the first and second circuits wherein the third circuit generates a first output signal and a second output signal having a logic relationship between the first, second, third and fourth inputs signals wherein the first output signal being at a first output state and the second output signal being at a second output state.

20030054589, Mar 20, 2003

Jan 18, 2002

10/051248

Yoshinari Matsuda - San Diego CA, US
Ikuo Sanwo - San Marcos CA, US
Mahyer Nejat - San Diego CA, US

Sony Corporation

H01L021/44
H01L021/48
H05K001/00
H01L023/48

438/108000, 257/693000, 361/777000

The invention is directed to a chip size package (“CSP”) configuration and method for arranging a CSP configuration which is simple to manufacture, and less costly. The invention includes a structure for a printed circuit board (“PCB”), having at least a single pad for a chip size package (“CSP”) which is square shape. The CSP pad then is rotated 45 degrees in a clockwise or counter clockwise direction from a perpendicular so as to form a diamond shape. Also included is at least a via having a circle shape and wherein the distance between an inner side of the rotated CSP pad, where the inner side is the side closest to the via, and the outer edge of the via is at least 0.1 mm.

47138270, Dec 15, 1987

Nov 10, 1986

6/929122

Donald K. Lauffer - Poway CA
Gregory H. Milby - San Diego CA
Paul M. Rostek - San Diego CA
Ikuo J. Sanwo - San Marcos CA

NCR Corporation - Dayton OH

H04L 2512

375 7

A terminator for a transceiver device for transmitting data signals to and receiving data signals from a second transceiver device over a transmission line therebetween. The terminator has a transmitter connected to the transmission line for transmitting data signals to the second transceiver device, a receiver connected to the transmission line for receiving data signals from the second transceiver device, a termination resistor connected to the transmission line for improving the transmission characteristics of the transmission line, and a switch device between the termination resistor and the transmission line. The switch device is closed for a portion of the time when the receiver is receiving data signals from the second transceiver device such that when it is closed the termination resistor is connected to the transmission line, and is open for the remainder to the time such that when it is open the termination resistor is not connected to the transmission line.

50308572, Jul 9, 1991

Aug 25, 1989

7/398563

Ikuo J. Sanwo - San Marcos CA
Gregory H. Milby - San Diego CA
Quynh-Giao X. Le - Escondido CA

NCR Corporation - Dayton OH

H03K 19017
H03K 19092
H03K 19096
G11C 1549

307475

In a high speed digital computer data transfer system, data bus voltage swings between logic high and logic low levels are reduced by defining minimum and maximum bus voltages which lie between said logic levels, thus lowering bus transition and hence data transfer times. The output voltages are converted to the proper logic levels with the aid of a differential (sense) amplifier. The preferred embodiment is implemented using complementary metal-oxide-semiconductor (CMOS) technology.

49530607, Aug 28, 1990

May 5, 1989

7/347976

Donald K. Lauffer - San Diego CA
Ikuo J. Sanwo - San Marcos CA
Paul M. Rostek - San Diego CA

NCR Corporation - Dayton OH

H05K 720

361388

A pin grid array package for carrying an integrated circuit chip having input/output leads. The pin grid array package includes a carrier having a centrally located opening for carrying the integrated circuit chip, a plurality of input/output pins spaced around the periphery of the centrally located opening, interconnect leads on the carrier for connecting selected ones of the input/output pins to selected leads of the integrated circuit chip, and heat sink material around the periphery of the input/output pins which serves as a cooling-fin for efficient integrated circuit chip heat removal. Each of the plurality of input/output pins is normal to the plane of the integrated circuit chip and extends through the carrier with a first portion extending away from a first side of the carrier and a second portion extending away from a second side of the carrier. The first portion of each input/output pin has a centrally located passage therein, and the second portion has a reduced pin portion for pluggable engagement with a centrally located passage of a similar input/output pin such that the pin grip array package is stackable.

56336020, May 27, 1997

Sep 14, 1995

8/528445

Ikuo J. Sanwo - San Marcos CA
Joseph D. Russell - La Mesa CA

NCR Corporation - Dayton OH

H03K 190185

326 73

A means of converting low voltage CMOS logic levels operating with a 3. 3 volts logic level to low voltage PECL logic levels operating with a 3. 3 volts supply voltage and a 0. 8 volts logic level. The circuit design is process insensitive, and the characteristics of the converter emulate the emitter follower outputs of ECL devices. The converter solves the signal ringing problems caused by open output conditions, and is less susceptible to electromagnetic interference.

49689053, Nov 6, 1990

Aug 25, 1989

7/398856

Ikuo J. Sanwo - San Marcos CA
Gregory H. Milby - San Diego CA
Quynh-Giao X. Le - Escondido CA

NCR Corporation - Dayton OH

H03K 1714

307475

An emitter coupled logic (ECL)-to-complementary metal-oxide-semiconductor (CMOS) logic level translator is temperature compensated to track temperature induced shifts in the ECL logic levels. The translator includes a differential amplifier with mid-range reference voltage. A reference voltage generator supplies the reference voltage to the differential amplifier and has a temperature sensitive transistor which changes the value of the circuit output (reference) voltage ambient with temperature shifts.