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Igor A Vikhliantsev

from Fremont, CA
Age ~59
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Also known as:
Igor A
Related to:
Natalian Vikhliantsev, 51
Connected to:
Jennifer L Vikjord, 50Ingrid E Viklund, 65Lars Viklund, 61Carolyn M Vikner, 46Lin M Vikner, 65Karthick Vikraman, 38Michele D Viksnes, 54Robert J Viktor, 92Sarah D Viktora, 37Brian K Viktorin, 61

Igor Vikhliantsev Phones & Addresses

  • Fremont, CA
  • 7224 Sleepy Creek Dr, San Jose, CA 95120 (408) 268-5134
  • Sunnyvale, CA
  • Santa Clara, CA
  • 7224 Sleepy Creek Dr, San Jose, CA 95120 (408) 828-4326

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Emails

i***[email protected]

Resumes

Resumes

Igor Vikhliantsev Photo 1

Distinguished Engineer

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Location:
7224 Sleepy Creek Dr, San Jose, CA 95120
Industry:
Semiconductors
Work:
eASIC since Jul 2008
Principal Engineer
LSI Dec 2000 - Jul 2008
Principal Engineer
LSI Logic International Sep 1996 - Nov 2000
Software Engineer
Volgograd State University Sep 1987 - Aug 1996
Associate professor, head of Discrete Math chair
Education:
Moscow Power Engineering Institute (Technical University) 1996 - 1998
Lomonosov Moscow State University (MSU) 1992 - 1992
PhD, Computer Science Волгоградский Государственный Университет 1987 - 1992
Master Degree in Math, Math/CS
Skills:
Structural Asic
Asic
Cad
Software Integration
Software Development
Front End Development
Backend
Software Design
Hardware Development
Hardware Design
Verilog
Rtl Design
Tcl
Tk
C++
Perl
Python
Design Compiler
Primetime
Formal Verification
Modelsim
Nc Verilog
Vlsi
Complexity Theory
Algorithms
Systemverilog
Hardware Architecture
Compilers
Integration
Eda
Static Timing Analysis
Semiconductors
Ncsim
Very Large Scale Integration
Application Specific Integrated Circuits
Interests:
Cooking
Exercise
Medicine
Electronics
Home Improvement
Reading
Crafts
Fitness
Music
Travel
Movies
Home Decoration
Health
Languages:
Italian
English
Russian
Igor Vikhliantsev Photo 2

Principal Engineer At Easic

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Position:
Principal Engineer at eASIC
Location:
San Francisco Bay Area
Industry:
Semiconductors
Work:
eASIC since Jul 2008
Principal Engineer
LSI Dec 2000 - Jul 2008
Principal Engineer
LSI Logic International Sep 1996 - Nov 2000
Software Engineer
Volgograd State University Sep 1987 - Aug 1996
Associate professor, head of Discrete Math chair
Education:
Moscow Power Engineering Institute (Technical University) 1996 - 1998
Lomonosov Moscow State University (MSU) 1992 - 1992
PhD, Computer Science Волгоградский Государственный Университет 1987 - 1992
Master Degree in Math, Math/CS
Skills:
Structural ASIC
ASIC
CAD
Software Integration
Software Development
Front-end Development
Backend
Software Design
Hardware Development
Hardware Design
Verilog
RTL design
TCL
Tk
C++
Perl
Python
Design Compiler
Primetime
Formal Verification
ModelSim
NC-Verilog
VLSI
Complexity Theory
Algorithms
Honor & Awards:
LSI Patent Champion 2001-2006
Languages:
English
Russian

Publications

Us Patents

Netlist Redundancy Detection And Global Simplification

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US Patent:
6848094, Jan 25, 2005
Filed:
Dec 31, 2002
Appl. No.:
10/334731
Inventors:
Alexander E. Andreev - San Jose CA, US
Igor A. Vikhliantsev - Sunnyvale CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 1750
US Classification:
716 12, 326 35, 716 1, 716 2, 716 14, 716 15
Abstract:
A method of global simplification of a netlist for an integrated circuit includes steps for generating a variable set representative of the inputs and outputs of logic elements in the netlist, re-ordering the inputs and corresponding outputs of the logic elements in the variable set, generating a key set representative of the inputs of the logic elements that are connected to the outputs, assigning names in the variable set that are representative of equivalent outputs having two or fewer essential variables to the same variable name, inserting names in the variable set representative of outputs having more than two essential variables, and assigning a value to each of the outputs having two or fewer essential variables.

Built-In Test For Multiple Memory Circuits

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US Patent:
6941494, Sep 6, 2005
Filed:
Dec 21, 2001
Appl. No.:
10/027311
Inventors:
Alexander E. Andreev - San Jose CA, US
Igor A. Vikhliantsev - Santa Clara CA, US
Lav D. Ivanovic - Cupertino CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G11C029/00
US Classification:
714718, 714736, 714 25
Abstract:
A memory test circuit includes a collar for coupling to a memory device for switching an address bus and a data bus of the memory device between an external circuit and the collar in response to a switching signal; and a controller coupled to the collar for generating the switching signal, a test vector, and control signals between the controller and the collar on as few as seven control lines for testing the memory device with the test vector. Multiple memory devices of various sizes may be tested with the same controller concurrently.

Clock Tree Synthesis With Skew For Memory Devices

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US Patent:
6941533, Sep 6, 2005
Filed:
Oct 21, 2002
Appl. No.:
10/277398
Inventors:
Alexander E. Andreev - San Jose CA, US
Igor A. Vikhliantsev - Sunnyvale CA, US
Ivan Pavisic - San Jose CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F017/50
US Classification:
716 6, 716 1, 716 7, 716 18
Abstract:
A method of synthesizing a clock tree for reducing peak power in an integrated circuit design includes partitioning a circuit design into a set of memory cells and a set of non-memory cells, partitioning the set of memory cells into segments, constructing a first clock tree having a first root vertex with a corresponding initial skew for each of the segments, constructing a second clock tree having a second root vertex with a corresponding initial skew for the set of non-memory cells, delay balancing the first root vertex and the second vertex clock tree, and inserting a clock buffer at a midpoint between the first root vertex and the second root vertex.

Process And Apparatus For Placement Of Cells In An Ic During Floorplan Creation

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US Patent:
7036102, Apr 25, 2006
Filed:
Oct 27, 2003
Appl. No.:
10/694208
Inventors:
Alexander E. Andreev - San Jose CA, US
Andrey A. Nikitin - Moscow, RU
Igor A. Vikhliantsev - Sunnyvale CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 17/50
US Classification:
716 7, 716 9, 716 10
Abstract:
Objects are placed in a rectangle and their coordinates of the objects and are adjusted to establish a substantially uniform density of objects in the rectangle. The evaluation of coordinates is performed by placing the wires between cells coordinates and adjusting the cell coordinates to connect the cells to the wires. The substantially uniform density is achieved by dividing the rectangle into first and second rectangles having equal free areas and into third and fourth rectangles having equal areas of objects. The coordinates of the objects are adjusted based on boundaries between the first and second rectangles and between the third and fourth rectangles.

Pseudo-Random One-To-One Circuit Synthesis

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US Patent:
7050582, May 23, 2006
Filed:
Jun 18, 2001
Appl. No.:
09/883733
Inventors:
Alexander E. Andreev - San Jose CA, US
Igor A. Vikhliantsev - Santa Clara CA, US
Ranko Scepanovic - San Jose CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H04K 1/00
H04L 9/00
US Classification:
380 28, 380268, 380 37, 380 29, 380 42, 380 46
Abstract:
A method of defining a transformation between an input signal and an output signal. The transformation may implement a pseudo-random one-to-one function that may be implemented in hardware and/or software or modeled in software. The method may comprise the steps of (A) allocating the input signal among a plurality of block input signals, (B) establishing a plurality of transfer functions where each transfer function may be configured to present a plurality of unique symbols as a block output signal responsive to said block input signal, and (C) concatenating the block output signals to form the output signal.

Method For Generating Tech-Library For Logic Function

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US Patent:
7062726, Jun 13, 2006
Filed:
Apr 30, 2003
Appl. No.:
10/426549
Inventors:
Alexander E. Andreev - San Jose CA, US
Igor A. Vikhliantsev - Sunnyvale CA, US
Anatoli A. Bolotov - Cupertino CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 17/50
US Classification:
716 1, 716 3, 716 18
Abstract:
The present invention is directed to a method for generating a tech-library for a logic function. A logic function has many representations. For each representation, a circuit for realizing the representation is decomposed into a combination of instances. An instance is a component logic circuit of a general logic circuit. There are pre-created tech-libraries for the instances. For example, a pre-created tech-library is created by categorizing tech-descriptions for primitive physical circuits based on a negation index. Thus, tech-descriptions for a circuit for realizing a representation are calculated from a combination of elements of the pre-created tech-libraries. Each calculated tech-description is compared with each existing element of a tech-library for the logic function. When a calculated tech-description has at least one marked parameter better or smaller than that of all existing elements of the tech-library for the logic function, the calculated tech-description is added to the tech-library. When the number of elements in the tech-library is at least twice larger than a limit, the number is reduced.

Controller Architecture For Memory Mapping

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US Patent:
7065606, Jun 20, 2006
Filed:
Sep 4, 2003
Appl. No.:
10/655191
Inventors:
Alexander E. Andreev - San Jose CA, US
Igor A. Vikhliantsev - Sunnyvale CA, US
Ranko Scepanovic - Saratoga CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 12/00
US Classification:
711102, 711170, 711202
Abstract:
The present invention is directed to a method and apparatus for mapping a customer memory onto a plurality of physical memories. The apparatus may include: (a) a plurality of physical memories onto which a customer memory may be mapped, each of physical memories having a data width of m blocks, the customer memory having a data width of k blocks, and k and m being integers; (b) an address controller, communicatively coupled to a plurality of physical memories, for receiving first address information of the customer memory, for outputting second address information to a plurality of physical memories, and for outputting index information; (c) a data input controller, communicatively coupled to the address controller and a plurality of physical memories, for receiving data of the customer memory and the index information, and for outputting data with a data width of m blocks to a plurality of physical memories; and (d) a data output controller, communicatively coupled to a plurality of physical memories and to the address controller though a delay unit, for receiving the index information, for receiving output, with a width of said m blocks, of a plurality of physical memories, and for outputting the customer memory with a width of said k blocks.

Integrated Circuit And Process For Identifying Minimum Or Maximum Input Value Among Plural Inputs

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US Patent:
7072922, Jul 4, 2006
Filed:
Dec 13, 2002
Appl. No.:
10/319219
Inventors:
Alexander E. Andreev - San Jose CA, US
Anatoli A. Bolotov - Cupertino CA, US
Igor Vikhliantsev - Sunnyvale CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 15/00
US Classification:
708207
Abstract:
Apparatus and process identifies a maximum or minimum value among a plurality of binary values on a plurality of a-bit wide wires in an integrated circuit module. An N-bit vector K is calculated based on n most significant bits of all a-bit binary signals, where N=2. M N-bit vectors K,. . . ,K_(M−1) are calculated based on the n most significant and the m least significant bits of all a-bit binary signals, where M is at least 2−1. A table is constructed from vectors K,. . . ,K(M−1) to create table vectors. A table vector is selected based on vector K, is used to derive a vector P, which in turn is used to select another table vector. The minimum or maximum binary value is identified from the two selected table vectors.
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Igor A Vikhliantsev from Fremont, CA, age ~59 Get Report