Ian Yeeon Lam

6345371, Feb 5, 2002

May 5, 1999

09/304958

Ian Lam - Fremont CA

Advanced Micro Devices Inc. - Sunnyvale CA

G11C 2900

714719, 714735, 714824

A method and apparatus are disclosed for testing the functionality of a queue structure. An input circuit is provided for inputting data into an input portion of the queue structure, while an output circuit is provided for retrieving data from an output portion of the queue structure. A comparison logic circuit compares the retrieved data with the input data to determine the integrity of the data that was stored in the queue structure and verify that the data from the output portion is identical to the data input to the queue. Various embodiments are disclosed for testing queue structure both in real time and in a test mode.

6442137, Aug 27, 2002

May 24, 1999

09/317143

Ching Yu - Santa Clara CA
Xiaohua Zhuang - Santa Clara CA
Bahadir Erimli - Campbell CA
John M. Chiang - San Jose CA
Shashank Merchant - Sunnyvale CA
Robert Williams - Cupertino CA
Edward Yang - San Jose CA
Chandan Egbert - San Jose CA
Vallath Nandakumar - Campbell CA
Ian Lam - Daly City CA
Eric Tsin-Ho Leung - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H04L 522

370232, 370468, 370229, 370429, 710310, 710311

A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802. 3) protocol that allocates a prescribed number of external memory bandwidth slots between high data rate ports based on the compared amount of network traffic on the respective ports. A scheduler within an external memory interface initially assigns memory access slots to the respective high data rate ports according to a prescribed sequence. If the scheduler subsequently detects that the network data traffic on a port having less slots is higher than the traffic on a port having more slots, the slots are swapped between the high data rate ports. Additionally, a clock multiplexer in one of the high data rate ports adjusts the data rate of the port dependent upon the number of slots assigned to that port. The swapping of bandwidth slots between the high data rate ports along with the adjustment of the port clock rate enables the efficient use of limited memory bandwidth resources.

6501734, Dec 31, 2002

May 24, 1999

09/317150

Ching Yu - Santa Clara CA
Xiaohua Zhuang - Santa Clara CA
Bahadir Erimli - Campbell CA
John M. Chiang - San Jose CA
Shashank Merchant - Sunnyvale CA
Robert Williams - Cupertino CA
Edward Yang - San Jose CA
Chandan Egbert - San Jose CA
Vallath Nandakumar - Campbell CA
Ian Lam - Daly City CA
Eric Tsin-Ho Leung - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H04J 116

370236, 370230, 370235, 370237

A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802. 3) protocol dynamically allocates external memory bandwidth slots between high data rate ports. An external memory interface determines if a high data rate port makes a request for a bandwidth slot and grants the request if made. The slot is taken from a selected group which is a subset of the total number of slots. If a request for the slot is not made, the external memory interface assigns the slot to another high data rate port. Lower data rate ports in the network switch are assigned fixed slots from those slots not from within the selected group of slots. The dynamic allocation of bandwidth slots between the high data rate port enables the efficient use of limited memory bandwidth resources.

6542512, Apr 1, 2003

Jul 2, 1999

09/346745

Jenny Liu Fischer - Mountain View CA, 94040
Ching Yu - Santa Clara CA, 95051
Jerry Chun-Jen Kuo - San Jose CA, 95123
Po-Shen Lai - San Jose CA, 95123
Autumn Jane Niu - Sunnyvale CA, 94086
Ian Lam - Fremont CA, 94538

H04L 1228

370412

A network switch in a packet switched network includes a plurality of network switch ports, each configured for sending and receiving data packets between a medium interface and the network switch. The network switch port includes an IEEE 802. 3 compliant transmit state machine and receive state machine configured for transmitting and receiving network data to and from a medium interface, such as a reduced medium independent interface, respectively. The network switch port also includes a memory management unit configured for selectively transferring the network data between the transmit and receive state machines and a random access transmit buffer and a random access receive buffer, respectively. The transmit state machine outputs a flush transmit buffer signal to the transmit memory management unit in response to a detected error in transmitting the transmit data. The transmit memory management unit, in response to the flush transmit buffer signal, sets an incremented transmit buffer pointer value to a buffer pointer value corresponding to a next transmit data stored in the transmit buffer.

6701489, Mar 2, 2004

May 7, 1999

09/306458

Ian Lam - Fremont CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 1750

716 4, 716 5

A network switch configured for switching data packets across multiple ports uses numerous digital registers to process signals in support of the switchs functionalities. The design parameters associated with these registers are readily modifiable by storing these parameters in a central storage system. These design parameters are automatically read into the source code of a hardware description language, whereby the values and definitions of the registers are modified without altering the source code. Accordingly, any source code requiring updated bit definition and default values is automatically initialized without concern over design mismatch.

6957270, Oct 18, 2005

Jan 16, 2001

09/760299

Bahadir Erimli - Campbell CA, US
Ian Lam - Fremont CA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G08F015/16

709235, 370235

A number of network devices that control the communication of data frames between stations in a network are cascaded together to support a number of network stations. When a first device receives a data frame destined for a port on a second device, the first device transfers the data frame to the second device. The second device stores receive port information transmitted with the data frame and processes the data frame. If the second device identifies a congestion condition associated with processing the data, the second device transmits the receive port information back to the first device. The first device then performs a flow control-related operation on the port identified by the receive port information.

7031305, Apr 18, 2006

May 24, 1999

09/317156

Ching Yu - Santa Clara CA, US
Xiaohua Zhuang - Santa Clara CA, US
Bahadir Erimli - Campbell CA, US
John M. Chiang - San Jose CA, US
Shashank Merchant - Sunnyvale CA, US
Robert Williams - Cupertino CA, US
Edward Yang - San Jose CA, US
Chandan Egbert - San Jose CA, US
Vallath Nandakumar - Campbell CA, US
Ian Lam - Daly City CA, US
Eric Tsin-Ho Leung - San Jose CA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

H04L 12/28

370389, 3703954, 370412, 370458, 370468

A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802. 3) protocol that flexibly assigns memory access slots to access an external memory according to programmable information. A scheduler within an external memory interface assigns the memory access slots to the respective network switch ports according to a programmed sequence written into an assignment table memory from an external programmable data storage device.

60291974, Feb 22, 2000

Dec 18, 1997

8/992920

Bahadir Erimli - Mountain View CA
Ian Lam - Daly City CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 1300

709223

An integrated multiport switch (IMS) in which an on-chip management information base (MIB) accumulation processor enables monitoring of a significantly larger number of MIB objects to be stored in external memory while minimizing, media access controller (MAC) complexity. A MAC for each port in the IMS outputs a MIB report for each transmission or reception of data according to a specific compressed format to a MIB engine that can be centrally located on the chip. The compression of the data that represents the monitored events enables conservation of the capacity of MAC buffer elements. The MIB report is immediately dispatched to the MIB engine upon receipt or transmission of a data frame. The MIB engine decodes the MIB report into a plurality of associated MIB objects. which are temporarily accumulated until the external memory is updated.