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I-Hsing Tan Phones & Addresses

  • 8099 Presidio Dr, Cupertino, CA 95014 (408) 996-8771

Work

Company: Fit optical interconnect technology 2016 Position: Director product marketing

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Uc Santa Barbara 1988 to 1992 Specialities: Electrical Engineering

Skills

Product Marketing • Product Development • Semiconductors • Product Management • Optics • Fiber Optics • Ic • R&D • Ethernet • Telecommunications • Cross Functional Team Leadership • Optoelectronics • Electronics • Product Launch • Semiconductor Industry • Optical Communications • Manufacturing • Engineering Management • Photonics • Product Lifecycle Management • Business Development • Soc • Strategic Partnerships • Optical Fiber • Analog • Program Management • Technical Marketing • Sensors • Wireless • Start Ups • Mixed Signal • Rf • Power Management • Research and Development • Solid State Lighting • Asic • Eda • Go To Market Strategy • Wireless Technologies • Application Specific Integrated Circuits

Languages

English • Mandarin • Taiwanese

Industries

Telecommunications

Resumes

Resumes

I-Hsing Tan Photo 1

Director Product Marketing

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Location:
San Francisco, CA
Industry:
Telecommunications
Work:
Fit Optical Interconnect Technology
Director Product Marketing

Avago Technologies 2008 - 2015
Segment Marketing Manager

Oplink Communications 2007 - 2008
Senior Director of Active Business Development and Plm

Jdsu 2003 - 2007
Product Marketing Manager

Axt 2001 - 2003
Vice President
Education:
Uc Santa Barbara 1988 - 1992
Doctorates, Doctor of Philosophy, Electrical Engineering
National Taiwan University 1984 - 1986
Master of Science, Masters, Electrical Engineering
National Chiao Tung University 1980 - 1984
Bachelors, Bachelor of Science, Electronics Engineering
Skills:
Product Marketing
Product Development
Semiconductors
Product Management
Optics
Fiber Optics
Ic
R&D
Ethernet
Telecommunications
Cross Functional Team Leadership
Optoelectronics
Electronics
Product Launch
Semiconductor Industry
Optical Communications
Manufacturing
Engineering Management
Photonics
Product Lifecycle Management
Business Development
Soc
Strategic Partnerships
Optical Fiber
Analog
Program Management
Technical Marketing
Sensors
Wireless
Start Ups
Mixed Signal
Rf
Power Management
Research and Development
Solid State Lighting
Asic
Eda
Go To Market Strategy
Wireless Technologies
Application Specific Integrated Circuits
Languages:
English
Mandarin
Taiwanese

Publications

Us Patents

Photodiode Assembly With Improved Electrostatic Discharge Damage Threshold

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US Patent:
20090283848, Nov 19, 2009
Filed:
May 13, 2008
Appl. No.:
12/119667
Inventors:
I-Hsing Tan - Cupertino CA, US
Shuping Shang - Shenzhen, CN
Oleg Bouevitch - Ottawa, CA
Assignee:
JDS Uniphase Corporation - Milpitas CA
International Classification:
H01L 29/866
US Classification:
257438, 257E29335
Abstract:
A photodiode with an improved electrostatic damage threshold is disclosed. A Zener or an avalanche diode is connected in parallel to a photodiode. Both diodes are integrated into the same photodiode housing. The diodes can be mounted on a common header or onto each other. An avalanche photodiode and an avalanche diode can be fabricated on a common semiconductor substrate. A regular p-n diode connected in series, cathode-to-cathode or anode-to-anode, to a Zener diode, forms a protection circuit which, when connected in parallel to a photodiode, provides a smaller electrical capacity increase as compared to a simpler circuit consisting just of a Zener or an avalanche diode.

High Speed Vcsel

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US Patent:
6658040, Dec 2, 2003
Filed:
Jul 28, 2000
Appl. No.:
09/627878
Inventors:
Syn-Yem Hu - San Jose CA
I-Hsing Tan - Cupertino CA
Assignee:
Agilent Technologies, Inc. - Palo Alto CA
International Classification:
H01S 5183
US Classification:
372 96
Abstract:
A vertical cavity surface emitting laser (VCSEL) has a top mirror structure with a surface, a light generation region, and a bottom mirror structure for reflecting light toward said top mirror structure. The VCSEL has a semiconductor portion with a surface that is disposed substantially planar with respect to the surface of the top mirror structure. At least one aperture-defining layer having an isolatable material is disposed in at least one of the bottom mirror structure and the top mirror structure. The aperture-defining layer has a conducting region, an insulating region having an aperture-defining surface for defining the conducting region, and a single trench adjacent to the insulating region for use in generating the insulating region. The trench having a continuous geometry for reducing the parasitic capacitance of the VCSEL.
I-Hsing Tan from Cupertino, CA Get Report