US Patent:
20080141086, Jun 12, 2008
Inventors:
Lin Huang - San Jose CA, US
Huaming Hu - Fremont CA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G01R 31/28
Abstract:
A scan chain planning method uses physical data with a hierarchical design to optimize chip level scan chains. Specifically, location data of physical blocks is used to determine optimal partitioning of the hierarchical design to balance chip level scan chains and reduce the number block scan ports by determining optimal locations for the block scan ports. Actual layout of the scan chains is based on the locations of the block scan ports and the number of scan elements determined by the method for each block scan chain.