Hown P Cheng

8390743, Mar 5, 2013

Aug 31, 2011

13/222111

Hown Cheng - Cupertino CA, US
Do Hwan Lim - San Jose CA, US
Byungdae Jeong - San Jose CA, US

Intersil Americas Inc. - Milpitas CA

H04N 7/14
H04N 9/64
H04N 7/18
H04N 9/74

348716, 348 1407, 348153, 348159, 348588

Systems and methods for the synchronization and display of video input signals. The input signals, associated with input channels, are received by a controller. On a frame-by-frame basis, the controller controls the writing of the input signals to, and the reading of the input signals from, a memory. A frame rate control module controls frame-level synchronization between the writing operations and reading operations of the controller so that when a frame is written to the memory is not simultaneously read from the memory. The controller writes video frames for each input channel to, and reads video frames for each input channel from, the memory on a channel-by-channel basis such that the video frames corresponding to each input channel are read and written independently of one another. This allows the input signals to be unsynchronized with one another without harming the writing operations, reading operations, and display of the input signals.

20120251085, Oct 4, 2012

Aug 31, 2011

13/222105

Hown Cheng - Cupertino CA, US
Do Hwan Lim - San Jose CA, US
Heejeong Ryu - Cupertino CA, US

H04N 5/91

386337, 386E05003

A video system including a plurality of video sources, a recording device, a memory, and a controller. The controller receives video frames from the video sources and includes a first and a second write control module, a read control module, and a frame rate control module. The first write control module includes a write pointer and writes a first video frame to a first frame buffer. The second write control module includes a second write pointer and writes a second video frame to a second frame buffer. The read control module includes a read pointer. The frame rate control module controls the reading of the first and second video frames based on a multiplexing order and a read memory location of the read pointer respecting a write memory location of the write pointer. The read control module outputs a multiplexed signal to the recording device according to the multiplexing order.

7246220, Jul 17, 2007

Jul 27, 2001

09/917312

Hown Cheng - Cupertino CA, US
Chenhui Feng - Sunnyvale CA, US

Magnum Semiconductor, Inc. - Milpitas CA

G06F 9/48

712228

In one embodiment of the present invention, a processing system for processing information efficiently and cost-effectively by switching between execution of time-critical and non-time-critical tasks includes a processing unit. The processing system further includes a first register group coupled to the processing unit and including a first set of registers, the processing unit reading the status of the first set of registers to execute time-critical tasks. The processing system further includes a second register group coupled to the processing unit and including a second set of registers, the second register group for updating the status of the second set of registers, the processing unit reading the status of the second set of registers to execute the non-time-critical tasks by avoiding saving the status of the first set of registers, wherein the processing unit switches between executing time-critical tasks and non-time-critical tasks efficiently and cost-effectively by avoiding saving status of the first or second set of registers.