Hiroyuki A Akatsu

6387782, May 14, 2002

Jun 6, 2001

09/875072

Hiroyuki Akatsu - Yorktown Heights NY
Omer H. Dokumaci - Poughkeepsie NY
Suryanarayan G. Hegde - New York NY
Yujun Li - Poughkeepsie NY
Rajesh Rengarajan - Poughkeepsie NY
Paul A. Ronsheim - Hopewell Junction NY

International Business Machines Corporation - Armonk NY
Infineon Technologies North America Corp. - San Jose CA

H01L 21336

438542, 438478, 438308

A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate. A low thermal budget is maintained because of the proximity of the as-implanted peak concentration to the interface and the presence of species implanted through the dielectric film and into the substrate.

6449202, Sep 10, 2002

Aug 14, 2001

09/929593

Hiroyuki Akatsu - Yorktown Heights NY
Louis L. Hsu - Fishkill NY
Jeremy K. Stephens - New Windsor NY
Daniel W. Storaska - Walden NY

International Business Machines Corporation - Armonk NY

G11C 700

365205, 365203

A direct sensing circuit and method for reading data from a memory cell connected to a bitline, with open bitline sensing without using a reference bitline signal, onto a data line in a data read operation. Prior to the data read operation, both the bitline and the data line are precharged to precharge voltages and a sense node is precharged to ground. A pFET device has its gate coupled to a signal developed on the bitline from the memory cell to detect and amplify the signal level thereof, and has its source coupled to a voltage source and its drain coupled to a sense node, such that the signal developed on the bitline determines the degree of turn-on of the pFET device. An nFET device has its gate coupled to the sense node to detect and amplify the signal level thereof, and has its drain coupled to the data line. When sensing a low data signal, the signal developed on the bitline causes subthreshold voltage leakage current through the pFET device to charge the gate of the nFET device which is floating to amplify the signal developed on the bitline to pull down the precharged data line. When sensing a high data signal, the pFET device and the nFET device remain inactivated, and the data line remains at its precharge high voltage.

6485894, Nov 26, 2002

Sep 29, 2000

09/675250

Hiroyuki Akatsu - Yorktown Heights NY
Franz X. Zach - Wappingers Falls NY

International Business Machines Corporation - Armonk NY

G03C 556

430327, 430313, 430317, 430311, 216 40

A method to self-align a lithographic pattern to a workpiece, the method including the steps of obtaining a workpiece having a predetermined pattern of features; modifying at least some of the features so that when a photoresist material is applied to the pattern, there is a substantial difference in reflectivity between two adjacent features, at least one of which has been modified; applying a photoresist material; masklessly exposing the photoresist material; developing the photoresist material, the substantial difference in reflectivity of the two adjacent features causing the developed photoresist material to reveal one adjacent feature but not the other.

6723611, Apr 20, 2004

Sep 10, 2002

10/241225

Hiroyuki Akatsu - Yorktown Heights NY
Oleg Gluschenkov - Wappingers Falls NY
Porshia S. Parkinson - Danbury CT
Ravikumar Ramachandran - Pleasantville NY
Helmut Horst Tews - Munich, DE

International Business Machines Corporation - Armonk NY

H01L 2120

438386, 438243, 438255

In the course of forming a trench capacitor or similar structure, the sidewalls of an aperture in a substrate are lined with a film stack containing a diffusion barrier; an upper portion of the outer layer is stripped, so that the upper and lower portions have different materials exposed; the lower portion of the film stack is stripped while the upper portion is protected by a hardmask layer; a diffusion step is performed in the lower portion while the upper portion is protected; and a selected material such as hemispherical grained silicon is deposited selectively on the lower portion while the exposed surface of the upper portion is a material on which the selected material forms poorly, so that the diffusing material penetrates and the selected material is formed only on the lower portion.

6724031, Apr 20, 2004

Jan 13, 2003

10/340999

Hiroyuki Akatsu - Yorktown Heights NY
Dureseti Chidambarrao - Weston CT
Ramachandra Divakaruni - Ossining NY
Jack Mandelman - Flat Rock NC
Carl J. Radens - LaGrangeville NY

International Business Machines Corporation - Armonk NY

H01L 27108

257302, 257301, 257305, 438241, 438242, 438243, 438246

A dynamic random access memory cell comprising: a trench capacitor formed in a silicon substrate; a vertical MOSFET formed in a silicon substrate above the trench capacitor, the vertical MOSFET having a gate electrode, a first source/drain region extending from a surface of the silicon substrate into the silicon substrate, a buried second source/drain region electrically contacting the trench capacitor, a channel region formed in the silicon substrate between the first source/drain region and the buried second source/drain region and a gate oxide layer disposed between the gate electrode and the channel region; the first source/drain region also belonging to an adjacent vertical MOSFET, the adjacent vertical MOSFET having a buried third source/drain region electrically connected to an adjacent trench capacitor, the buried second and third source/drain regions extending toward one another; and a punch through prevention region disposed between the buried second and third source/drain regions.

6806138, Oct 19, 2004

Jan 21, 2004

10/707890

Kangguo Cheng - Beacon NY
Hiroyuki Akatsu - Yorktown Heights NY
Rama Divakaruni - Ossining NY

International Business Machines Corporation - Armonk NY

H01L 218242

438243, 438255, 438244, 438386, 438249

The capacitance of deep trench capacitors is enhanced by increasing the surface area of the doped region of the trench to be used for one electrode of the capacitor. After formation of the deep trench and a collar on an upper region of the trench, and after optional bottling of the trench, hemispherical silicon grain (HSG) is deposited on a lower region of the trench. The HSG is then oxidized, along with that portion of the silicon substrate not covered by HSG, to form a roughened surface in the trench, thereby enhancing the trench capacitance. Oxidation of the HSG and the substrate occurs simultaneously with formation of the buried plate, and the formed oxide may be stripped along with the collar, thereby providing a simpler and more robust capacitance enhancement scheme.

6806177, Oct 19, 2004

Nov 21, 2003

10/719861

Jay W. Strane - Chester NY
Hiroyuki Akatsu - Yorktown Heights NY
David M. Dobuzinsky - New Windsor NY

International Business Machines Corporation - Armonk NY

H01L 2144

438597, 438242, 438586

A method for forming high-density self-aligned contacts and interconnect structures in a semiconductor device. A dielectric layer thick enough to contain both interconnect and contact structures is formed on a substrate. A patterned hardmask is formed on the dielectric layer to define both the interconnect and contact structures. The openings for interconnect features are first formed by partially etching the dielectric layer selective to the hardmask. A second mask (e. g. , a resist) is used to define the contact openings, and the dielectric layer is etched through the second mask, also selective to the hardmask, to expose the diffusion regions to be contacted. The patterned hardmask is used to help define the contact openings. Conductive material is then deposited in the openings which results in contacts and interconnects that are self-aligned. By first forming the openings for both interconnect and contacts, savings in processing steps may be obtained.

6809027, Oct 26, 2004

Jun 6, 2002

10/165264

Jay W. Strane - Chester NY
Hiroyuki Akatsu - Yorktown Heights NY
David M. Dobuzinsky - New Windsor NY

International Business Machines Corporation - Armonk NY

H01L 214763

438637, 438243

A method for forming high-density self-aligned contacts and interconnect structures in a semiconductor device. A dielectric layer thick enough to contain both interconnect and contact structures is formed on a substrate. A patterned hardmask is formed on the dielectric layer to define both the interconnect and contact structures. The openings for interconnect features are first formed by partially etching the dielectric layer selective to the hardmask. A second mask (e. g. , a resist) is used to define the contact openings, and the dielectric layer is etched through the second mask, also selective to the hardmask, to expose the diffusion regions to be contacted. The patterned hardmask is used to help define the contact openings. Conductive material is then deposited in the openings which results in contacts and interconnects that are self-aligned. By first forming the openings for both interconnect and contacts, savings in processing steps may be obtained.