Hieu Thi Tran

6396742, May 28, 2002

Jul 28, 2000

09/627917

George J. Korsh - Redwood City CA
Sakhawat M. Khan - Los Altos CA
Hieu Van Tran - San Jose CA

Silicon Storage Technology, Inc. - Sunnyvale CA

G11C 1604

36518522, 36518503, 36518518, 36518529

In accordance with an embodiment of the present invention, a method for testing a multilevel memory includes: performing an erase operation to place a plurality of memory cells in an erased state; programming a state of each cell in a group of the plurality of cells to within a first range of voltages; if a state of each of one or more of the cells in the group of cells does not verify to within the first range of voltages, identifying at least the one or more cells as failing; and if a state of each cell in the group of cells verifies to within the first range of voltages: applying a predetermined number of programming pulses to further program the state of each cell in the group of cells to within a second range of voltages; and verifying whether a state of each cell in the group of cells is programmed beyond the second range of voltages.

6867638, Mar 15, 2005

Jan 10, 2002

10/044273

William John Saiki - Mountain View CA, US
Hieu Van Tran - San Jose CA, US
Sakhawat M. Khan - Los Altos CA, US

Silicon Storage Technology, Inc. - Sunnyvale CA

G05F001/10

327536

A high voltage generator provides high voltage signals with different regulated voltage levels. A charge pump generates the high voltage, and includes a quadrature phase forward and backward Vt-canceling high-voltage self-biasing charge pump with a powerup-assist diode. A high voltage series regulator generates the high voltage supply levels, and includes slew rate enhancement and trimmable diode regulation. A nested loop regulator eliminates shunt regulation.

6967524, Nov 22, 2005

Nov 16, 2004

10/990786

William John Saiki - Mountain View CA, US
Hieu Van Tran - San Jose CA, US
Sakhawat M. Khan - Los Altos CA, US

Silicon Storage Technology, Inc. - Sunnyvale CA

G05F001/10

327541

A high voltage generator provides high voltage signals with different regulated voltage levels. A charge pump generates the high voltage, and includes a quadrature phase forward and backward Vt-canceling high-voltage self-biasing charge pump with a powerup-assist diode. A high voltage series regulator generates the high voltage supply levels, and includes slew rate enhancement and trimmable diode regulation. A nested loop regulator eliminates shunt regulation.

7061295, Jun 13, 2006

Nov 16, 2004

10/991301

William John Saiki - Mountain View CA, US
Hieu Van Tran - San Jose CA, US
Sakhawat M. Khan - Los Altos CA, US

Silicon Storage Technology, Inc. - Sunnyvale CA

G06F 1/04

327295, 331 57

An oscillator that can be used within a high voltage generation and regulation system for non-volatile memory. The system may comprise a charge pump that may have at least one pump and an oscillator. In one aspect the oscillator provides clock signals to the pump. The output of the oscillator may be disabled without turning off the clock generation. The oscillator may be a ring oscillator. In one aspect, the ring oscillator and the output stage may comprise inverters with a capacitor coupled to the output of the inverter. In one aspect, the ratio of the capacitors in the ring oscillator to the capacitor in the output stage determine the phase shift between the two clock signals. In another aspect, the capacitance of the capacitors are identical and a bias applied the ring oscillator and the output stage are radioed to adjust the phase between the two clock signals.

7631231, Dec 8, 2009

Apr 19, 2006

11/407602

Sang Thanh Nguyen - Union City CA, US
Hieu Van Tran - San Jose CA, US
Hung O. Nguyen - Fremont CA, US
Phil Klotzkin - Springfield NJ, US

Silicon Storage Technology, Inc. - Sunnyvale CA

G11C 29/00
G01R 31/28
G11C 7/00

714718, 714734, 365201

In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan cell connected to each bond pad, allowing for rapid connectivity testing of flash memory chips in accordance with testing standards such as the JTAG standard. The invention further includes methods in which the pins and/or memory cells of a flash memory chip are sequentially sent a series of data so as to test the connectivity of portions of the IC. The sequentially-sent data is then retrieved and compared to the original data. Discrepancies between these sets of data thus highlight connectivity problems in the IC.

8020055, Sep 13, 2011

Dec 2, 2009

12/629302

Sang Thanh Nguyen - Union City CA, US
Hieu Van Tran - San Jose CA, US
Hung O. Nguyen - Fremont CA, US
Phil Klotzkin - Springfield NJ, US

Silicon Storage Technology, Inc. - Sunnyvale CA

G11C 29/00
G11C 7/00

714718, 365201

In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan cell connected to each bond pad, allowing for rapid connectivity testing of flash memory chips in accordance with testing standards such as the JTAG standard. The invention further includes methods in which the pins and/or memory cells of a flash memory chip are sequentially sent a series of data so as to test the connectivity of portions of the IC. The sequentially-sent data is then retrieved and compared to the original data. Discrepancies between these sets of data thus highlight connectivity problems in the IC.

20060017084, Jan 26, 2006

Jul 22, 2004

10/897045

Feng Gao - Sunnyvale CA, US
Changyuan Chen - Sunnyvale CA, US
Vishal Sarin - Cupertino CA, US
William Saiki - Mountain View CA, US
Hieu Tran - San Jose CA, US
Dana Lee - Santa Clara CA, US

H01L 29/76

257296000

An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and spaced apart from the channel region of the first capacitor. The second capacitor is substantially identical to the first capacitor and is formed in the same semiconductor substrate. The gate electrode of the first capacitor is electrically connected to the first region of the second capacitor and the gate electrode of the second capacitor is electrically connected to the first region of the first capacitor. In this manner, the capacitors are connected in an anti-parallel configuration. A capacitor which has high capacitance densities, low process complexity, ambipolar operation, low voltage and temperature coefficient, low external parasitic resistance and capacitance and good matching characteristics for use in analog designs that can be integrated with existing semiconductor processes results.

20090096507, Apr 16, 2009

Nov 13, 2008

12/270604

Feng Gao - Sunnyvale CA, US
Changyuan Chen - Sunnyvale CA, US
Vishal Sarin - Cupertino CA, US
William John Saiki - Mountain View CA, US
Hieu Van Tran - San Jose CA, US
Dana Lee - Santa Clara CA, US

Silicon Storage Technology, Inc. - Sunnyvale CA

H03K 3/01

327534

An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and spaced apart from the channel region of the first capacitor. The second capacitor is substantially identical to the first capacitor and is formed in the same semiconductor substrate. The gate electrode of the first capacitor is electrically connected to the first region of the second capacitor and the gate electrode of the second capacitor is electrically connected to the first region of the first capacitor. In this manner, the capacitors are connected in an anti-parallel configuration. A capacitor which has high capacitance densities, low process complexity, ambipolar operation, low voltage and temperature coefficient, low external parasitic resistance and capacitance and good matching characteristics for use in analog designs that can be integrated with existing semiconductor processes results.