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Herve G Duprez

from San Francisco, CA
Age ~63
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Also known as:
Herve Te Duprez
Phone and address:
448 Douglass St, San Francisco, CA 94114
Related to:
William C PfeiferDonald E Chaney, 71Patricia W Chaney, 72Lisa K Pfeifer, 54Chaney E ChaneyRonald E Chaney, 68
Connected to:
Daniel J Duprez, 35Michael W Duprez, 74Jasmin C Duprie, 43Charles M Dupriest, 35Clint D Dupriest, 45Donald Dupriest, 89James Dupriest, 62John G Dupriest, 47Karen L Dupriest, 66Leona C Dupriest, 74

Herve Duprez Phones & Addresses

  • 448 Douglass St, San Francisco, CA 94114
  • 181 Divisadero St, San Francisco, CA 94117
  • Campbell, CA
  • Sunnyvale, CA

Work

Company: Salesforce.com Jul 2009 Position: Business system analyst consultant

Education

School / High School: PMI Project Management Institute 2009 Specialities: Project Management Professional (PMP)

Skills

Crm • Project Management • Salesforce.com • Business Intelligence • Business Process • Enterprise Software • Business Analysis • Business Objects • Management • Cross Functional Team Leadership • Erp • Agile Methodologies • Outsourcing • Quality Assurance • Databases • Analytics • Cloud Computing • Customer Relationship Management • Software Development Life Cycle • Sap • Testing • Sap Products • Enterprise Resource Planning • Software Documentation • Analysis • Sdlc • Data Analysis

Languages

French

Ranks

Certificate: Mba International Operations. Icam Polytechnical Engineering

Interests

French Native • Education • Citizen

Industries

Computer Software

Resumes

Resumes

Herve Duprez Photo 1

Director Sales Analytics

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Location:
1 Market St, San Francisco, CA 94105
Industry:
Computer Software
Work:
Salesforce.com since Jul 2009
Business System Analyst Consultant
Taproot Foundation May 2009 - Jun 2010
Business System Analyst Volunteer
Autodesk Inc. 2005 - 2009
Siebel Project Implementation Manager
Autodesk Inc. 2003 - 2005
Siebel Project Development Lead/Senior Business Systems Analyst
Autodesk Inc. 2002 - 2003
SAP Project Development Lead/Senior Business Systems Analyst
Education:
PMI Project Management Institute 2009
European University of America 1985 - 1986
MBA, International OperationsEuropean University of America is an extension of ISG (Institut Superieur de Gestion) Paris, France. Institut catholique d'Arts et Métiers 1980 - 1984
Engineer, Poytechnical Engineering, Computer Sciences major Scrum Alliance - Danube Technologies
Skills:
Crm
Project Management
Salesforce.com
Business Intelligence
Business Process
Enterprise Software
Business Analysis
Business Objects
Management
Cross Functional Team Leadership
Erp
Agile Methodologies
Outsourcing
Quality Assurance
Databases
Analytics
Cloud Computing
Customer Relationship Management
Software Development Life Cycle
Sap
Testing
Sap Products
Enterprise Resource Planning
Software Documentation
Analysis
Sdlc
Data Analysis
Interests:
French Native
Education
Citizen
Languages:
French
Certifications:
Mba International Operations. Icam Polytechnical Engineering

Business Records

Name / Title
Company / Classification
Phones & Addresses
Herve Duprez
President
HERVE DUPREZ CONSULTING, INC
Business Consulting Services
448 Douglas St, San Francisco, CA 94114
448 Douglass St, San Francisco, CA 94114

Publications

Us Patents

Method For Labelling Polygons

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US Patent:
51134519, May 12, 1992
Filed:
Oct 16, 1989
Appl. No.:
7/422332
Inventors:
David C. Chapman - Campbell CA
Herve G. Duprez - Campbell CA
Assignee:
VLSI Technology, Inc. - San Jose CA
International Classification:
G06K 900
G06K 934
G06K 946
G06K 920
US Classification:
382 8
Abstract:
A method for labelling polygons of a geometric layout which includes the steps of scanning a geometric layout during a first scan line pass to detect objects which form a polygon, processing the scan line at each occurrence of an event to detect the objects which contact the scan line, assigning temporary numbers and root designators to the objects which contact the scan line in accordance with a sorting criterion, updating the temporary numbers assigned to the objects to keep the temporary number associated with the earliest root designator of each separately detected polygon, and renaming each object which forms a part of the same polygon with a common label. The step of updating includes the steps of numbering each object in a polygon with a temporary number assigned to a root object of the polygon, and storing, in a sorted order, the root objects which lose their status as root objects during the step of updating.

Method For Verifying Circuit Layout Design

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US Patent:
54503310, Sep 12, 1995
Filed:
Jan 24, 1992
Appl. No.:
7/825490
Inventors:
Pei Lin - San Jose CA
Herve G. Duprez - Campbell CA
Assignee:
VLSI Technology, Inc. - San Jose CA
International Classification:
G06F 1560
US Classification:
364490
Abstract:
The present invention is directed to methods to assist designing integrated circuits by verifying that design constraints (e. g. , minimum path width) are satisfied between two arbitrary nodes of a circuit layout. In an exemplary embodiment, a method for designing an integrated circuit layout by verifying that predetermined design constraints are satisfied for an arbitrary path defined by at least two nodes, comprises the steps of labeling all polygons of the integrated circuit layout with a name which corresponds to a layer of the integrated circuit layout in which each polygon is located, creating a file of polygons which includes polygons located along the arbitrary path, and determining whether polygons located along the arbitrary path satisfy predetermined design constraints specified for that path.
Control profile
Herve G Duprez from San Francisco, CA, age ~63 Get Report