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Hens C Vanderschoot

from Portland, OR
Age ~61
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Also known as:
Hens D Vanderschoot, He Vanderschoot, Christopher Vanderschoot Hens, Hans C Vandershoot, Hens T, Vanderschoot Hens, Vanderschoot He
Phone and address:
11170 Eden Ct, Portland, OR 97223
(503) 968-8295
Related to:
Priscilla A Stjohn, 77Conley WorcesterSophia N Vanderschoot, 27Victoria Murray, 61Joke Vanderschoot, 92Robert Dicus, 37
Connected to:
Aaron J Vanderplaats, 51Adrian T Vanderspek, 65Ainslie A Vandersluis, 57Alyssa M Vanderpool, 33Amee Vanderpool, 50Amy S Vandersip, 58Ann G Vanderslice, 88Anne M Vanderploeg, 58Barbara A Vandersloot, 81Brandon W Vanderschaaf, 44

Hens Vanderschoot Phones & Addresses

  • 11170 Eden Ct, Portland, OR 97223 (503) 968-8295
  • 1170 SW Eden Ct, Tigard, OR 97223 (503) 968-8295
  • 1850 68Th St, Lincoln City, OR 97367
  • Beaverton, OR
  • Des Moines, IA
  • 11170 SW Eden Ct, Portland, OR 97223 (503) 475-2449

Work

Company: Tektronix Feb 13, 2018 Position: Hw and sw design engineer

Education

Degree: Master of Science, Masters School / High School: Portland State University 1991 to 1995 Specialities: Electronics Engineering

Skills

Rtl Design • Logic Synthesis • Physical Design • System Architecture • Testing • Verilog • Asic • Hardware Architecture • Microprocessors • Fpga • Eda • Processors • Ic • Semiconductors • Soc • Debugging • Static Timing Analysis

Languages

English

Emails

h***[email protected]

Industries

Electrical/Electronic Manufacturing

Resumes

Resumes

Hens Vanderschoot Photo 1

Hw And Sw Design Engineer

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Location:
11170 southwest Eden Ct, Tigard, OR 97223
Industry:
Electrical/Electronic Manufacturing
Work:
Tektronix
Hw and Sw Design Engineer
Microsoft May 2015 - Aug 2017
Senior Design Engineer
Northwest Logic Nov 2013 - May 2015
Senior Design Engineer
Neofocal Systems Mar 2011 - Nov 2013
Senior Design Engineer
Nvidia Jan 2009 - Mar 2011
Senior Hardware Engineer
Education:
Portland State University 1991 - 1995
Master of Science, Masters, Electronics Engineering Colorado State University 1983 - 1986
Bachelors, Bachelor of Science In Electrical Engineering, Engineering George School
Portland State University
Masters, Master of Science In Electrical Engineering, Vlsi Design, Architecture
Skills:
Rtl Design
Logic Synthesis
Physical Design
System Architecture
Testing
Verilog
Asic
Hardware Architecture
Microprocessors
Fpga
Eda
Processors
Ic
Semiconductors
Soc
Debugging
Static Timing Analysis
Languages:
English

Publications

Us Patents

Method And Apparatus For A Burst Write In A Shared Bus Architecture

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US Patent:
6842837, Jan 11, 2005
Filed:
Feb 13, 2001
Appl. No.:
09/784274
Inventors:
Mark Peting - Tigard OR, US
Hens Vanderschoot - Tigard OR, US
Assignee:
Digeo, Inc. - Kirkland WA
International Classification:
G06F 1200
US Classification:
711168, 711 5, 711167, 711169, 711173, 710 35, 710 36, 710 37, 710 39, 710 52, 710 58, 36518904, 365194, 365203
Abstract:
A method and apparatus for a burst mode write in a shared bus architecture comprising detecting a write data burst, determining if at least one memory unit is available to receive the write data burst, writing the write data burst to the at least one memory unit if the at least one memory unit is available to receive data. Storing a first portion of the write data burst in a buffer, concurrently with activating the at least one memory unit to receive data, if the at least one memory unit is not available to receive data; writing a second portion of the write data burst to the at least one memory unit when the at least one memory unit is available to receive data, and writing the first portion of the write data burst from the buffer to the at least one memory unit after writing the second portion of the write data burst.

Checkpointed Buffer For Re-Entry From Runahead

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US Patent:
20130297911, Nov 7, 2013
Filed:
May 3, 2012
Appl. No.:
13/463627
Inventors:
Guillermo J. Rozas - Los Gatos CA, US
Paul Serris - San Jose CA, US
Brad Hoyt - Portland OR, US
Sridharan Ramakrishnan - Hillsboro OR, US
Hens Vanderschoot - Tigard OR, US
Ross Segelken - Portland OR, US
Darrell Boggs - Aloha OR, US
Magnus Ekman - Alameda CA, US
Assignee:
NVIDIA CORPORATION - Santa Clara CA
International Classification:
G06F 9/30
US Classification:
712205, 712E09016
Abstract:
Embodiments related to re-dispatching an instruction selected for re-execution from a buffer upon a microprocessor re-entering a particular execution location after runahead are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic, one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic, and scheduler logic for scheduling the retrieved instruction for execution. The example scheduler logic includes a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.

Method And Apparatus For Compensating For Thermal Drift In A Logic Circuit

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US Patent:
60345586, Mar 7, 2000
Filed:
Jul 17, 1997
Appl. No.:
8/895722
Inventors:
Hens Christopher Vanderschoot - Tigard OR
Timothy M. Wasson - Portland OR
Assignee:
Credence Systems Corporation - Fremont CA
International Classification:
H03H 1126
US Classification:
327277
Abstract:
A system for compensating for thermal drift of an output signal (OUT1) produced by a logic circuit in response to an input CLOCK signal after a temperature dependent delay includes a variable delay circuit, an oscillator and a digital phase lock controller. The delay circuit delays the OUT1signal to produce a compensated output signal (OUT2) with a variable delay controlled by input CONTROL data. The oscillator generates an output signal (OSC. sub. -- OUT) having a period also controlled by the input CONTROL data which is substantially proportional to the sum of the temperature dependent delay of the logic circuit and the delay of the variable delay circuit. The digital phase lock controller continually monitors the period of the OSC. sub. -- OUT signal and adjusts the CONTROL data so that the period of the OSC. sub. -- OUT signal remains substantially constant.

Lazy Runahead Operation For A Microprocessor

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US Patent:
20170199778, Jul 13, 2017
Filed:
Mar 27, 2017
Appl. No.:
15/470602
Inventors:
- Santa Clara CA, US
Ross Segelken - Portland OR, US
Guillermo J. Rozas - Los Gatos CA, US
Alexander Klaiber - Mountain View CA, US
James van Zoeren - Albuquerque NM, US
Paul Serris - San Jose CA, US
Brad Hoyt - Portland OR, US
Sridharan Ramakrishnan - Hillsboro OR, US
Hens Vanderschoot - Tigard OR, US
Darrell D. Boggs - Aloha OR, US
International Classification:
G06F 11/07
G06F 9/30
G06F 9/38
G06F 15/78
Abstract:
Embodiments related to managing lazy runahead operations at a microprocessor are disclosed. For example, an embodiment of a method for operating a microprocessor described herein includes identifying a primary condition that triggers an unresolved state of the microprocessor. The example method also includes identifying a forcing condition that compels resolution of the unresolved state. The example method also includes, in response to identification of the forcing condition, causing the microprocessor to enter a runahead mode.

Queued Instruction Re-Dispatch After Runahead

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US Patent:
20140189313, Jul 3, 2014
Filed:
Dec 28, 2012
Appl. No.:
13/730407
Inventors:
- Santa Clara CA, US
Alexander Klaiber - Mountain View CA, US
James van Zoeren - Albuquerque NM, US
Paul Serris - San Jose CA, US
Brad Hoyt - Portland OR, US
Sridharan Ramakrishnan - Hillsboro OR, US
Hens Vanderschoot - Tigard OR, US
Ross Segelken - Portland OR, US
Darrell D. Boggs - Aloha OR, US
Magnus Ekman - Alameda CA, US
Aravindh Baktha - Portland OR, US
David Dunn - Sammamish WA, US
Assignee:
NVIDIA CORPORATION - Santa Clara CA
International Classification:
G06F 9/30
US Classification:
712214
Abstract:
Various embodiments of microprocessors and methods of operating a microprocessor during runahead operation are disclosed herein. One example method of operating a microprocessor includes identifying a runahead-triggering event associated with a runahead-triggering instruction and, responsive to identification of the runahead-triggering event, entering runahead operation and inserting the runahead-triggering instruction along with one or more additional instructions in a queue. The example method also includes resuming non-runahead operation of the microprocessor in response to resolution of the runahead-triggering event and re-dispatching the runahead-triggering instruction along with the one or more additional instructions from the queue to the execution logic.

Lazy Runahead Operation For A Microprocessor

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US Patent:
20140164736, Jun 12, 2014
Filed:
Dec 7, 2012
Appl. No.:
13/708645
Inventors:
- Santa Clara CA, US
Alexander Klaiber - Mountain View CA, US
James van Zoeren - Albuquerque NM, US
Paul Serris - San Jose CA, US
Brad Hoyt - Portland OR, US
Sridharan Ramakrishnan - Hillsboro OR, US
Hens Vanderschoot - Tigard OR, US
Ross Segelken - Portland OR, US
Darrell D. Boggs - Aloha OR, US
Magnus Ekman - Alameda CA, US
Assignee:
NVIDIA CORPORATION - Santa Clara CA
International Classification:
G06F 15/78
US Classification:
712 43
Abstract:
Embodiments related to managing lazy runahead operations at a microprocessor are disclosed. For example, an embodiment of a method for operating a microprocessor described herein includes identifying a primary condition that triggers an unresolved state of the microprocessor. The example method also includes identifying a forcing condition that compels resolution of the unresolved state. The example method also includes, in response to identification of the forcing condition, causing the microprocessor to enter a runahead mode.

Instruction Categorization For Runahead Operation

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US Patent:
20140164738, Jun 12, 2014
Filed:
Dec 7, 2012
Appl. No.:
13/708544
Inventors:
- Santa Clara CA, US
Guillermo J. Rozas - Los Gatos CA, US
Alexander Klaiber - Mountain View CA, US
James van Zoeren - Albuquerque NM, US
Paul Serris - San Jose CA, US
Brad Hoyt - Portland OR, US
Sridharan Ramakrishnan - Hillsboro OR, US
Hens Vanderschoot - Tigard OR, US
Ross Segelken - Portland OR, US
Darrell D. Boggs - Aloha OR, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 9/30
US Classification:
712205, 712229
Abstract:
Embodiments related to methods and devices operative, in the event that execution of an instruction produces a runahead-triggering event, to cause a microprocessor to enter into and operate in a runahead without reissuing the instruction are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic for retrieving an instruction, scheduling logic for issuing the instruction retrieved by the fetch logic for execution, and runahead control logic. The example runahead control logic is operative, in the event that execution of the instruction as scheduled by the scheduling logic produces a runahead-triggering event, to cause the microprocessor to enter into and operate in a runahead mode without reissuing the instruction, and carry out runahead policies while the microprocessor is in the runahead mode that governs operation of the microprocessor and cause the microprocessor to operate differently than when not in the runahead mode.

Managing Potentially Invalid Results During Runahead

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US Patent:
20140136891, May 15, 2014
Filed:
Nov 14, 2012
Appl. No.:
13/677085
Inventors:
- Santa Clara CA, US
Guillermo J. Rozas - Los Gatos CA, US
Alexander Klaiber - Mountain View CA, US
James van Zoeren - Albuquerque NM, US
Paul Serris - San Jose CA, US
Brad Hoyt - Portland OR, US
Sridharan Ramakrishnan - Hillsboro OR, US
Hens Vanderschoot - Tigard OR, US
Ross Segelken - Portland OR, US
Darrell D. Boggs - Aloha OR, US
Magnus Ekman - Alameda CA, US
Assignee:
NVIDIA CORPORATION - Santa Clara
International Classification:
G06F 11/07
US Classification:
714 15
Abstract:
Embodiments related to managing potentially invalid results generated/obtained by a microprocessor during runahead are provided. In one example, a method for operating a microprocessor includes causing the microprocessor to enter runahead upon detection of a runahead event. The example method also includes, during runahead, determining that an operation associated with an instruction referencing a storage location would produce a potentially invalid result based on a value of an architectural poison bit associated with the storage location and performing a different operation in response.
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Hens C Vanderschoot from Portland, OR, age ~61 Get Report