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Jim H Fulford

from Marianna, FL
Age ~64
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Also known as:
Henry J Fulford, Henry Jim Fulford, James Fulford
Related to:
Brian E Fulford, 39Christina FulfordDaniel J Fulford, 40Michelle FulfordWendy C Fulford, 63Patricia G Graham, 83Lynn M Otto, 38Daniel FulfordH Fulford
Connected to:
Angel A Fulford, 35Brad K Fulford, 59Carlos R Fulford, 61Charles H Fulford, 61Clint E Fulford, 51Cory S Fulford, 37Daryle J Fulford, 51Emma R Fulford, 29Frank H Fulford, 88

Jim Fulford Phones & Addresses

  • Marianna, FL
  • Greenwood, FL
  • 2901 Keating Ave, Burnsville, MN 55337 (952) 808-8920
  • 4046 Pine Bluff Dr, Meridian, ID 83642 (208) 608-5924
  • Austin, TX
  • Bloomington, MN
  • 11015 Bexley Ln, Austin, TX 78739

Emails

r***[email protected]

Business Records

Name / Title
Company / Classification
Phones & Addresses
Mr. Jim Fulford, Jr
General Manager
Fulford Hardware Inc
Survival Products & Supplies
874 2nd Avenue E, Owen Sound, ON N4K 2H3
(519) 376-7729, (519) 376-0957
Jim Fulford
General Manager
Fulford Hardware Inc
Survival Products & Supplies
(519) 376-7729, (519) 376-0957

Publications

Us Patents

Semiconductor Constructions

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US Patent:
8274081, Sep 25, 2012
Filed:
Mar 22, 2010
Appl. No.:
12/728942
Inventors:
Vladimir Mikhalev - Boise ID, US
Jim Fulford - Meridian ID, US
Yongjun Jeff Hu - Boise ID, US
Gordon A. Haller - Boise ID, US
Lequn Liu - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 29/04
H01L 33/16
US Classification:
257 57, 257E21135, 257E21615, 438424, 438482, 438365, 438766
Abstract:
Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400 C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.

Semiconductor Processing Methods, And Methods Of Forming Isolation Structures

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US Patent:
20120329231, Dec 27, 2012
Filed:
Sep 4, 2012
Appl. No.:
13/603100
Inventors:
Vladimir Mikhalev - Boise ID, US
Jim Fulford - Meridian ID, US
Yongjun Jeff Hu - Boise ID, US
Gordon A. Haller - Boise ID, US
Lequn Liu - Boise ID, US
Assignee:
MICRON TECHNOLOGY, INC. - Boise ID
International Classification:
H01L 21/762
H01L 21/336
US Classification:
438296, 438433, 257E21409, 257E21551
Abstract:
Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400 C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.

Semiconductor Device Having A Liner Defining The Depth Of An Active Region, And Fabrication Thereof

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US Patent:
61001481, Aug 8, 2000
Filed:
Dec 19, 1997
Appl. No.:
8/995023
Inventors:
Mark I. Gardner - Cedar Creek TX
Derick Wristers - Austin TX
Jim H. Fulford - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 21336
US Classification:
438305
Abstract:
A semiconductor device having a liner which defines the depth of an active region and a process for fabricating such a device is disclosed. The use of a liner can, for example, allow the formation of shallower source/drain regions and enhance the performance of the device. In accordance with one aspect of the process, a semiconductor device is formed by forming a gate electrode over a substrate and forming a liner in the substrate adjacent to the gate electrode. An active region is then formed in the substrate, whereby the depth of an active region is defined by the liner. The liner can be formed from several materials including, for example, n-type and p-type dopants and/or oxygen-bearing species.

Method Of Forming Semiconductor Devices Using Gate Electrode Length And Spacer Width For Controlling Drivecurrent Strength

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US Patent:
58638245, Jan 26, 1999
Filed:
Dec 18, 1997
Appl. No.:
8/993755
Inventors:
Mark I. Gardner - Cedar Creek TX
Jim H. Fulford - Austin TX
Anthony Toprac - Austin TX
Assignee:
Advanced Micro Devices - Austin TX
International Classification:
H01L 2576
H01L 21265
US Classification:
438303
Abstract:
A semiconductor device having a controlled drive current strength is produced by varying spacer width to accommodate any variation in gate electrode length from a desired value. After formation of the gate electrode on a substrate, the length is measured and compared to a desired value. Based on any differences between the measured and desired values, the width of spacer is determined in order to counteract the variation in gate electrode length. This results in maintaining the desired channel length after dopant implanting, to provide the desired drive current strength. The present process permits close control over the drive current strength of semiconductor devices and also decreased variation within and between lots and corresponding increases in productivity.

Method For Forming Film Stacks With Multiple Planes Of Transistors Having Different Transistor Architectures

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US Patent:
20210013107, Jan 14, 2021
Filed:
Oct 28, 2019
Appl. No.:
16/665599
Inventors:
- Tokyo, JP
Jim Fulford - Marianna FL, US
Assignee:
TOKYO ELECTRON LIMITED - Tokyo
International Classification:
H01L 21/8238
H01L 27/092
H01L 29/06
H01L 29/423
H01L 29/786
H01L 21/02
H01L 21/306
H01L 21/308
H01L 29/66
Abstract:
Three-dimensional integration can overcome scaling limitations by increasing transistor density in volume rather than area. To provided gate-all-around field-effect-transistor devices with different threshold voltages and doping types on the same substrate, methods are provided for growing adjacent nanosheet stacks having channels with different doping profiles. In one example, a first nanosheet stack is formed having channels with first doping characteristics. Then the first nanosheet stack is etched, and a second nanosheet stack is formed in plane with the first nanosheet stack. The second nanosheet stack has channels with different doping characteristics. This process can be repeated for additional nanosheet stacks. In another example, the formation of the nanosheet stacks with channels having different doping characteristics is performed by restricting layer formation to predefined locations using a patterned layer (e.g., a conformal oxide layer) that limits epitaxial growth to exposed regions of the substrate where the patterned layer is etched away.
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Jim H Fulford from Marianna, FL, age ~64 Get Report