Henry Sheng Chen

6580156, Jun 17, 2003

Apr 4, 2002

10/115013

Akira Ito - Irvine CA
Henry Kuoshun Chen - Irvine CA

Broadcom Corporation - Irvine CA

H01L 2358

257665, 257529, 257173, 257209, 438215

An integrated fuse has regions of different doping located within a fuse neck. The integrated fuse includes a polysilicon layer and a silicide layer. The polysilicon layer includes first and second regions having different types of dopants. In one example, the first region has an N-type dopant and the second region has a P-type dopant. The polysilicon layer can also include a third region in between the first and second regions, which also has a different dopant. During a fusing event, a distribution of temperature peaks around the regions of different dopants. By locating regions of different dopants within the fuse neck, agglomeration of the silicide layer starts reliably within the fuse neck (for example, at or near the center of the fuse neck) and proceeds toward the contact regions. An improved post fuse resistance distribution and an increased minimum resistance value in the post fuse resistance distribution is realized compared to conventional polysilicon fuses.

6770948, Aug 3, 2004

Apr 9, 2003

10/409584

Akira Ito - Irvine CA
Henry Kuoshun Chen - Irvine CA

Broadcom Corporation - Irvine CA

H01L 2900

257529, 257173, 257209, 257665, 257910, 1022024, 3612751, 438467, 438600, 438601

An integrated fuse has regions of different doping located within a fuse neck. The integrated fuse includes a polysilicon layer and a silicide layer. The polysilicon layer includes first and second regions having different types of dopants. In one example, the first region has an N-type dopant and the second region has a P-type dopant. The polysilicon layer can also include a third region in between the first and second regions, which also has a different dopant. During a fusing event, a distribution of temperature peaks around the regions of different dopants. By locating regions of different dopants within the fuse neck, agglomeration of the silicide layer starts reliably within the fuse neck (for example, at or near the center of the fuse neck) and proceeds toward the contact regions. An improved post fuse resistance distribution and an increased minimum resistance value in the post fuse resistance distribution is realized compared to conventional polysilicon fuses.

6950355, Sep 27, 2005

Dec 18, 2001

10/020208

Surya Battacharya - Irvine CA, US
Ming Chen - Mission Viejo CA, US
Liming Tsau - Irvine CA, US
Henry Chen - Irvine CA, US

Broadcom Corporation - Irvine CA

G11C007/00

365201, 365154

A method for testing a semiconductor wafer. An array of probes is coupled to the semiconductor wafer. Then a voltage difference is applied across a plurality of adjacent metal line pairs (e. g. , wordline and/or bitline pairs) of one or more SRAM arrays of at least one die. Application of the voltage difference induces failure of metal stringers or defects between the adjacent lines. Additionally, the voltage can be applied across respective pairs of substantially all parallel metal lines of the one or more SRAM arrays of more that one die of the semiconductor wafer.

7009832, Mar 7, 2006

Mar 14, 2005

11/078511

Henry KuoShun Chen - Irvine CA, US
Akira Ito - Irvine CA, US

Broadcom Corporation - Irvine CA

H01G 4/228

3613061, 361309, 361329, 257306, 257310, 29 2541

A capacitor including a first and second component capacitor structure disposed on a substrate. A component capacitor structure includes an upright arm, a transverse arm, and a via. The upright arm has a top end and a bottom end that extend at substantially right angles to a central axis of the upright arm. The transverse arm has a left and right end that extend at substantially right angles to a central axis of the transverse arm. The upright arm and the transverse arm intersect to form a cross-like pattern and the top, bottom, left and right ends all extend in the same rotary direction. The via is electrically coupled to an area of intersection of the upright and transverse arms.

7009891, Mar 7, 2006

May 19, 2005

11/132335

Vincent Chen - Newport Coast CA, US
Henry Chen - Irvine CA, US
Liming Tsau - Irvine CA, US
Jay Shiau - Irvine CA, US
Surya Battacharya - Irvine CA, US
Akira Ito - Irvine CA, US

Broadcom Corporation - Irvine CA

H01L 29/00
G11C 7/00

36518901, 257530, 257532, 438131, 438467, 438600, 3652257

A one-time programming memory element, capable of being manufactured in a 0. 13 μm or below CMOS technology, having a capacitor, or transistor configured as a capacitor, with an oxide layer capable of passing direct gate tunneling current. Also included is a write switch, having first and second switches coupled to the capacitor, and a read switch also coupled to the capacitor. The capacitor/transistor is one-time programmable as an anti-fuse by application of a program voltage across the oxide layer via the write switch to cause direct gate tunneling current to rupture the oxide layer to form a conductive path having resistance of approximately hundreds of ohms or less.

7151660, Dec 19, 2006

Jan 4, 2006

11/324221

Henry KuoShun Chen - Irvine CA, US
Akira Ito - Irvine CA, US

Broadcom Corporation - Irvine CA

H01G 4/228

3613061, 361309, 361329, 257306, 257310, 29 2541

A capacitor including a first and second component capacitor structure disposed on a substrate. A component capacitor structure includes a first arm, a second arm, and a via. The first arm has a first end and a second end. The second arm has a third end and a fourth end. The first arm and the second arm intersect and the first, second, third and fourth ends all extend in the same rotary direction. The via is electrically coupled to an area of intersection of the first and second arms.

7161213, Jan 9, 2007

Aug 5, 2004

10/911720

Akira Ito - Irvine CA, US
Henry K. Chen - Irvine CA, US

Broadcom Corporation - Irvine CA

H01L 27/01
H01L 21/338

257349, 438173

A P-type metal oxide semiconductor (PMOS) device can include an N-well that does not extend completely throughout the active region of the PMOS device. For example, the PMOS device can be fabricated using a masking step to provide an N-well having an inner perimeter and an outer perimeter. The inner perimeter of the N-well surrounds at least a portion of the active region of the PMOS device. According to an embodiment, the inner perimeter of the N-well surrounds the entire active region. The PMOS device can include a deep N-well in contact with the N-well.

7227238, Jun 5, 2007

Jun 21, 2004

10/871569

Akira Ito - Irvine CA, US
Henry K. Chen - Irvine CA, US

Broadcom Corporation - Irvine CA

H01L 29/00

257529, 257173, 257209, 257665, 257910, 1022024, 3612751, 438467, 438600, 438601

An integrated fuse has regions of different doping located within a fuse neck. The integrated fuse includes a polysilicon layer and a silicide layer. The polysilicon layer includes first and second regions having different types of dopants. In one example, the first region has an N-type dopant and the second region has a P-type dopant. The polysilicon layer can also include a third region in between the first and second regions, which also has a different dopant. During a fusing event, a distribution of temperature peaks around the regions of different dopants. By locating regions of different dopants within the fuse neck, agglomeration of the silicide layer starts reliably within the fuse neck (for example, at or near the center of the fuse neck) and proceeds toward the contact regions. An improved post fuse resistance distribution and an increased minimum resistance value in the post fuse resistance distribution is realized compared to conventional polysilicon fuses.