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Helena R Calendar

from Beaverton, OR
Age ~53
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Also known as:
Helena Rigmor Calendar, Helena R Calender, Hugo R Calendar
Phone and address:
6743 SW 162Nd Dr, Beaverton, OR 97007
Related to:
Johanna M Calendar, 84Richard L Calendar, 84Johanna M Calendar, 50Hugo R Calendar, 55
Connected to:
Brandon J Calender, 37Quinn K Calendine, 34Ruth A Calendine, 60Natalie C Calendo, 37Danielle G Calenti, 47Jessica G Calentine, 72Joyce A Calentine, 69Nicholas Y Calenti, 37Manlio Calentti, 52Robert J Calenzo, 59

Helena Calendar Phones & Addresses

  • 6743 SW 162Nd Dr, Beaverton, OR 97007
  • Missouri City, TX
  • 1001 Slate Way, Monument, CO 80132 (719) 487-1893
  • Milpitas, CA
  • San Jose, CA
  • Mountain View, CA

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Emails

h***[email protected]

Resumes

Resumes

Helena Calendar Photo 1

Senior Principal Layout Designer

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Location:
6743 southwest 162Nd Dr, Beaverton, OR 97007
Industry:
Semiconductors
Work:
United Memories Inc since Jan 2001
Senior Layout DRAM designer
Mosel Vitelic Mar 1997 - Jan 2001
Layout designer
ABB Combustion Engineering Nuclear Systems Aug 1996 - Feb 1997
Electrical Engineer
ABB Atom - Vasteras, Sweden Sep 1995 - Aug 1996
Electrical Engineer
Holmen Paper AB Jan 1986 - Jan 1993
Technician
Education:
Uppsala University 1990 - 1995
M.S, Engineering Physics
Skills:
Dram
Semiconductors
Cmos
Ic
Lvs
Flash Memory
Analog
Cadence
Interests:
Earned A 1St Dan Black Belt In 2012
Enjoy Motorcycle Riding
Owned A 1971 Honda 350Cc
Helena Calendar Photo 2

Helena Calendar

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Helena Calendar Photo 3

Helena Calendar Monument, CO

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Work:
United Memories Inc
Colorado Springs, CO
2001 to Aug 2013
Senior IC Layout DRAM designer
Mosel Vitelic Inc
San Jose, CA
1997 to 2001
IC Layout and Circuit designer
ABB Atom
Windsor, CT
Aug 1996 to Feb 1997
Engineer
ABB Atom

1995 to 1997
Engineer
Holmen Paper AB
Norrkping
Jun 1986 to 1993
Also worked as an analyst
Education:
Uppsala University
Nov 1995
M.S. in Engineering Physics
University of Uppsala
1990 to 1992
Management
Helena Calendar Photo 4

Helena Calendar Monument, CO

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Work:
United Memories Inc

2001 to 2000
Senior Layout DRAM designer
DRAM Circuit and Layout
San Jose, CA
1997 to 2001
Circuit and Layout designer
ABB Combustion Engineering Nuclear Systems
Windsor, CT
Aug 1996 to Feb 1997
Electrical Engineer
ABB Atom
Vsters
Sep 1995 to Aug 1996
Electrical Engineer
Holmen Paper AB

Jun 1986 to 1993
Technician
Education:
Uppsala University
Uppsala
Jan 1995
M.S. in Engineering Physics

Business Records

Name / Title
Company / Classification
Phones & Addresses
Helena Calendar
Acaru LLC
Software Developemnt & Related Activitie
2405 Countrybrook, San Jose, CA 95132

Publications

Us Patents

Programmable Latches That Include Non-Volatile Programmable Elements

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US Patent:
61634921, Dec 19, 2000
Filed:
Oct 23, 1998
Appl. No.:
9/178445
Inventors:
Nikolas Sredanovic - Mountain View CA
Helena Calendar - Mountain View CA
Assignee:
Mosel Vitelic, Inc. - Hsin chu
International Classification:
G11C 700
US Classification:
3652257
Abstract:
A non-volatile programmable latch (210) has a fuse (F1) connected between a non-ground voltage terminal (212) and an output terminal (OUT). A NMOS transistor (110) is connected between the output terminal and ground. An inverter (120) has an input connected to the output terminal and an output connected to the gate of the NMOS transistor. A diode connects the output terminal to the non-ground voltage terminal (212) to prevent a charge build up on the output terminal when the power is off.

Programmable Latches That Include Non-Volatile Programmable Elements

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US Patent:
62662902, Jul 24, 2001
Filed:
Mar 1, 2000
Appl. No.:
9/516336
Inventors:
Nikolas Sredanovic - Mountain View CA
Helena Calendar - Mountain View CA
Assignee:
Mosel Vitelic, Inc.
International Classification:
G11C 700
US Classification:
3652257
Abstract:
A non-volatile programmable latch (210) has a fuse (F1) connected between a non-ground voltage terminal (212) and an output terminal (OUT). A NMOS transistor (110) is connected between the output terminal and ground. An inverter (120) has an input connected to the output terminal and an output connected to the gate of the NMOS transistor. A diode connects the output terminal to the non-ground voltage terminal (212) to prevent a charge build up on the output terminal when the power is off.

Programmable Latches That Include Non-Volatile Programmable Elements

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US Patent:
62227769, Apr 24, 2001
Filed:
Sep 25, 2000
Appl. No.:
9/669780
Inventors:
Nikolas Sredanovic - Mountain View CA
Helena Calendar - Mountain View CA
Assignee:
Mosel Vitelic, Inc. - Hsin Chu
International Classification:
G11C 700
US Classification:
36518901
Abstract:
A non-volatile programmable latch (210) has a fuse (F1) connected between a non-ground voltage terminal (212) and an output terminal (OUT). A NMOS transistor (110) is connected between the output terminal and ground. An inverter (120) has an input connected to the output terminal and an output connected to the gate of the NMOS transistor. A diode connects the output terminal to the non-ground voltage terminal (212) to prevent a charge build up on the output terminal when the power is off.

Initialization Of Non-Volatile Programmable Latches In Circuits In Which An Initialization Operation Is Performed

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US Patent:
60848030, Jul 4, 2000
Filed:
Oct 23, 1998
Appl. No.:
9/178197
Inventors:
Nikolas Sredanovic - Mountain View CA
Helena Calendar - Mountain View CA
Assignee:
Mosel Vitelic, Inc. - Hsin Chu
International Classification:
G11C 1604
US Classification:
36518905
Abstract:
A non-volatile programmable latch (110) in an integrated circuit (310) is initialized by an initialization signal (SET). At least a portion of the initialization signal is generated in response to a command to the circuit to perform a circuit initialization operation. In some embodiments, the circuit is a synchronous dynamic random access memory (SDRAM), or a synchronous graphics random access memory (SGRAM). The command is a mode register set command (MRS). The command is received when a predetermined period of time has elapsed after power was turned on. Waiting for the predetermined period of time before initializing the latch allows the voltage powering the latch to develop so that the latch can be initialized reliably.

Programmable Latches That Include Non-Volatile Programmable Elements

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US Patent:
62400347, May 29, 2001
Filed:
Sep 25, 2000
Appl. No.:
9/669992
Inventors:
Nikolas Sredanovic - Mountain View CA
Helena Calendar - Mountain View CA
Assignee:
Mosel Vitelic, Inc.
International Classification:
G11C 700
US Classification:
3652257
Abstract:
A non-volatile programmable latch (210) has a fuse (F1) connected between a non-ground voltage terminal (212) and an output terminal (OUT). A NMOS transistor (110) is connected between the output terminal and ground. An inverter (120) has an input connected to the output terminal and an output connected to the gate of the NMOS transistor. A diode connects the output terminal to the non-ground voltage terminal (212) to prevent a charge build up on the output terminal when the power is off.
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Helena R Calendar from Beaverton, OR, age ~53 Get Report