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Hector P Flores

from Colorado Springs, CO
Age ~69
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Also known as:
Hector Paul Flores, Hector P Hores
Phone and address:
11986 Hanging Valley Way, Colorado Springs, CO 80921
(719) 531-7801
Related to:
Elias Flores, 25Maria D Flores, 63Doemiko Flores, 42Sandra F Botts, 55Hanne Flores, 50Mary Flores
Connected to:
Abegail Flores, 35Abel Flores, 61Adalberto Flores, 40Adaly Flores, 35Adele D Flores, 93Adena M Flores, 42Africa Flores, 46Ailyn Flores, 46Aira T Flores, 29Al Flores, 54

Hector Flores Phones & Addresses

  • 11986 Hanging Valley Way, Colorado Springs, CO 80921 (719) 531-7801
  • Colorado Spgs, CO
  • Sunnyvale, CA
  • San Jose, CA
  • Yorktown, VA

Professional Records

Medicine Doctors

Hector Flores Photo 1

Hector A. Flores

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Specialties:
Thoracic Surgery, Vascular Surgery
Work:
El Paso Southwestern Cardiovascular Associates
1600 Medical Ctr Dr STE 212, El Paso, TX 79902
(915) 532-3977 (phone), (915) 532-5866 (fax)
Education:
Medical School
University of Texas Medical School at San Antonio
Graduated: 2003
Procedures:
Thoracoscopy
Abdominal Aortic Aneurysm
Coronary Artery Bypass
Hernia Repair
Pacemaker and Defibrillator Procedures
Removal Procedures on the Lungs and Pleura
Conditions:
Abdominal Aortic Aneurysm
Abdominal Hernia
Aortic Aneurism
Breast Disorders
Cholelethiasis or Cholecystitis
Languages:
English
Spanish
Description:
Dr. Flores graduated from the University of Texas Medical School at San Antonio in 2003. He works in El Paso, TX and specializes in Thoracic Surgery and Vascular Surgery. Dr. Flores is affiliated with Del Sol Medical Center, Hospitals Of Providence East Camp, Hospitals Of Providence Sierra Campus and Las Palmas Medical Center.
Hector Flores Photo 2

Hector Flores

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Specialties:
Family Medicine
Work:
Family Care Specialists
815 Washington Blvd, Montebello, CA 90640
(323) 728-3955 (phone), (323) 728-6905 (fax)
Education:
Medical School
University of California, Davis School of Medicine
Graduated: 1981
Conditions:
Abnormal Vaginal Bleeding
Acne
Acute Bronchitis
Acute Conjunctivitis
Acute Pharyngitis
Languages:
English
Spanish
Description:
Dr. Flores graduated from the University of California, Davis School of Medicine in 1981. He works in Montebello, CA and specializes in Family Medicine. Dr. Flores is affiliated with Beverly Hospital and White Memorial Medical Center.
Hector Flores Photo 3

Hector L. Flores

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Specialties:
Family Medicine
Work:
Blue Island Medical Group
1802 W Chicago Ave STE 2, Chicago, IL 60622
(773) 278-2998 (phone), (773) 278-2997 (fax)
Education:
Medical School
Universidad Central del Caribe School of Medicine
Graduated: 1987
Conditions:
Acute Bronchitis
Acute Sinusitis
Acute Upper Respiratory Tract Infections
Allergic Rhinitis
Anxiety Phobic Disorders
Languages:
English
Spanish
Description:
Dr. Flores graduated from the Universidad Central del Caribe School of Medicine in 1987. He works in Chicago, IL and specializes in Family Medicine.

Business Records

Name / Title
Company / Classification
Phones & Addresses
Hector Flores
Owner
H & H Towing Service
Automotive Services, Nec, Nsk
1038 Pepitone Ave, San Jose, CA 95110
Hector Sanchez Flores
President
NATIONAL COMPADRES NETWORK, INC
Nonclassifiable Establishments · Membership Organization
1550 The Alameda STE 303, San Jose, CA 95126
3129 S Hacienda Blvd, Whittier, CA 91745
Hector Flores
Corporate Secretary
M-PULSE MICROWAVE, INC
Mfg Semiconductors/Related Devices · Semiconductor and Related Device Manufacturing
576 Charcot Ave, San Jose, CA 95131
(408) 432-1480
Hector Flores
Flores Contracting
Stamped Concrete · Concrete Driveway · Fencing · Handyman Service · Remodeling · Bathroom & Kitchen Remodeling
3717 Macbeth Dr, San Jose, CA 95127
(408) 930-2663
Hector Flores
Director
Pacesetter Cde, Inc
Venture Capital Companies · Nonclassifiable Establishments
(214) 263-5982
Hector Flores
Director
Iha
Nonclassifiable Establishments
300 Lakeside Dr, Oakland, CA 94612
500 12 St, Oakland, CA 94607
Hector Flores
SOUTHEASTERN OHIO CENTER, INC
Hector Flores
TOLEDO JEEP HISPANIC ASSOCIATION

Publications

Us Patents

Fabricating A Semiconductor With An Insulative Coating

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US Patent:
54418984, Aug 15, 1995
Filed:
Dec 29, 1994
Appl. No.:
8/363732
Inventors:
John G. Richards - San Jose CA
Hector Flores - San Jose CA
Wendell B. Sander - Los Gatos CA
Assignee:
Micro Technology Partners - San Jose CA
International Classification:
H01L 2900
US Classification:
437 15
Abstract:
An electrical apparatus having a top and a bottom is described. A right side portion comprised of a first substrate of semiconductor material is provided. A left side portion of a second substrate of semiconductor material comprising an integrated circuit is provided. A middle portion between the right side portion and the left side portion is provided. The middle portion is comprised of an insulative coating. A metallic interconnecting structure is provided that electrically couples the first substrate of the right side portion to the integrated circuit of the left side portion. The metallic interconnecting structure extends over the insulative material of the middle portion. A top portion comprised of the insulative material is provided that covers the integrated circuit, the metallic interconnecting structure, the left side portion, the right side portion, and the middle portion. The top portion and the middle portion sandwich the metallic interconnecting structure. A substantially planar first metallic pad is provided for a first connection to external circuitry.

Resistor Fabrication

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US Patent:
61211192, Sep 19, 2000
Filed:
May 29, 1997
Appl. No.:
8/865357
Inventors:
John G. Richards - San Jose CA
Hector Flores - San Jose CA
Assignee:
Chipscale, Inc. - San Jose CA
International Classification:
H01L 2178
H01L 21301
H01L 2146
US Classification:
438462
Abstract:
The fabrication of a resistor structure is described. A resistive region is formed over the top of a substrate. Trenches are formed from the top side of the substrate in scribe line regions where the wafer is to be separated to form resistor modules. Contact layers are formed over the top side of the substrate and are electrically coupled to each end of the resistive region, respectively. The contact layers are also formed over the sidewalls of the trenches. The wafer is separated through the trenches, creating resistor modules having sidewall contact regions.

Semiconductor Fabrication With Contact Processing For Wrap-Around Flange Interface

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US Patent:
55571492, Sep 17, 1996
Filed:
Mar 24, 1995
Appl. No.:
8/409994
Inventors:
John G. Richards - San Jose CA
Wendell B. Sander - Los Gatos CA
Donald P. Richmond - Palo Alto CA
Hector Flores - San Jose CA
Assignee:
ChipScale, Inc. - San Jose CA
International Classification:
H01L 2348
H01L 2352
US Classification:
257779
Abstract:
A flange interface for wrap-around contact regions formed in fabricating semiconductor devices provides for a durable and reliable electrical bond. A first layer having a first material is formed over the first side of a wafer. A trench is formed from the second side of the wafer such that a portion of the first layer becomes exposed in the trench. A second layer having a second material is formed over the second side of the wafer such that a portion of the second layer contacts the portion of the first layer exposed in the trench. The wafer is separated through the trench. The trench may be formed by sawing the second side of the wafer in an area where the trench is to be formed. The wafer may then be etched such that the trench is formed.

Electrical Apparatus With A Metallic Layer Coupled To A Lower Region Of A Substrate And A Metallic Layer Coupled To A Lower Region Of A Semiconductor Device

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US Patent:
57898170, Aug 4, 1998
Filed:
Nov 15, 1996
Appl. No.:
8/749422
Inventors:
John Gareth Richards - San Jose CA
Hector Flores - San Jose CA
Wendell B. Sander - Los Gatos CA
Assignee:
Chipscale, Inc. - San Jose CA
International Classification:
H01L 2941
H01L 29868
H01L 2315
US Classification:
257724
Abstract:
An electrical apparatus having a first substrate, a first metallic layer, a semiconductor device, a second metallic layer, and a metallic interconnecting structure is described. The first substrate is of a semiconductor material and has an upper region and a lower region. The substrate provides an electrical path between the upper region and the lower region. The first metallic layer is coupled to the lower region of the substrate. The first metallic layer provides a first external electrical connection. The semiconductor device has an upper region and a lower region. The second metallic layer is coupled to the lower region of the semiconductor device. The second metallic layer provides a second external electrical connection. The metallic interconnecting structure electrically couples the upper region of the first substrate to the upper region of the semiconductor device. A bridge apparatus is also described.

Gallium Arsenide Planar Tunnel Diode Method

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US Patent:
47463988, May 24, 1988
Filed:
Jun 18, 1987
Appl. No.:
7/063376
Inventors:
Hormoz M. Motamedi - San Jose CA
John G. Richards - San Jose CA
Hector H. Flores - San Jose CA
Assignee:
FEI Microwave, Inc. - Sunnyvale CA
International Classification:
B44C 122
H01L 2158
H01L 2160
C03C 1500
US Classification:
156644
Abstract:
A gallium arsenide tunnel diode is fabricated using planar techniques from a wafer of gallium arsenide that has been heavily doped to form a P region. Tin is plated onto an exposed section of a surface of the wafer and then melted to cause individual tin atoms to diffuse only a few atomic layers into the wafer, creating a heavily doped N region. Metal contact layers are then formed over the tin and on the opposite surface of the wafer. An oxidation inhibitor is used during the plating and a scavenging agent is used during the melting to insure intimate contact between the tin and the wafer.

Fabricating A Semiconductor With An Insulative Coating

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US Patent:
54440092, Aug 22, 1995
Filed:
Dec 23, 1994
Appl. No.:
8/363733
Inventors:
John G. Richards - San Jose CA
Hector Flores - San Jose CA
Wendell B. Sander - Los Gatos CA
Assignee:
Micro Technology Partners - San Jose CA
International Classification:
H01L 2900
US Classification:
437 51
Abstract:
An electrical apparatus having a top and a bottom is described. A right side portion comprised of a first substrate of semiconductor material is provided. A left side portion of a second substrate of semiconductor material comprising an integrated circuit is provided. A middle portion between the right side portion and the left side portion is provided. The middle portion is comprised of an insulative coating. A metallic interconnecting structure is provided that electrically couples the first substrate of the right side portion to the integrated circuit of the left side portion. The metallic interconnecting structure extends over the insulative material of the middle portion. A top portion comprised of the insulative material is provided that covers the integrated circuit, the metallic interconnecting structure, the left side portion, the right side portion, and the middle portion. The top portion and the middle portion sandwich the metallic interconnecting structure. A substantially planar first metallic pad is provided for a first connection to external circuitry.

Method Of Making A Semiconductor Device With A Metallic Layer Coupled To A Lower Region Of A Substrate And Metallic Layer Coupled To A Lower Region Of A Semiconductor Device

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US Patent:
54551870, Oct 3, 1995
Filed:
Nov 1, 1994
Appl. No.:
8/331783
Inventors:
John G. Richards - San Jose CA
Hector Flores - San Jose CA
Assignee:
Micro Technology Partners - San Jose CA
International Classification:
H01L 21302
H01L 2144
H01L 2148
H01L 2176
US Classification:
437 62
Abstract:
An electrical apparatus having a first substrate, a first metallic layer, a semiconductor device, a second metallic layer, and a metallic interconnecting structure is described. The first substrate is of a semiconductor material and has an upper region and a lower region. The substrate provides an electrical path between the upper region and the lower region. The first metallic layer is coupled to the lower region of the substrate. The first metallic layer provides a first external electrical connection. The semiconductor device has an upper region and a lower region. The second metallic layer is coupled to the lower region of the semiconductor device. The second metallic layer provides a second external electrical connection. The metallic interconnecting structure electrically couples the upper region of the first substrate to the upper region of the semiconductor device. A bridge apparatus is also described.

Electrical Apparatus With A Metallic Layer Coupled To A Lower Region Of A Substrate And Metallic Layer Coupled To A Lower Region Of A Semiconductor Device

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US Patent:
52801942, Jan 18, 1994
Filed:
Sep 4, 1992
Appl. No.:
7/940763
Inventors:
John G. Richards - San Jose CA
Hector Flores - San Jose CA
Wendell B. Sander - Los Gatos CA
Assignee:
Micro Technology Partners - San Jose CA
International Classification:
H01L 2944
H01L 2308
US Classification:
257724
Abstract:
An electrical apparatus having a first substrate, a first metallic layer, a semiconductor device, a second metallic layer, and a metallic interconnecting structure is described. The first substrate is of a semiconductor material and has an upper region and a lower region. The substrate provides an electrical path between the upper region and the lower region. The first metallic layer is coupled to the lower region of the substrate. The first metallic layer provides a first external electrical connection. The semiconductor device has an upper region and a lower region. The second metallic layer is coupled to the lower region of the semiconductor device. The second metallic layer provides a second external electrical connection. The metallic interconnecting structure electrically couples the upper region of the first substrate to the upper region of the semiconductor device. A bridge apparatus is also described.

Isbn (Books And Publications)

La Respuesta Peronista

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Author

Hector Alberto Flores

ISBN #

9500622076

Biochemistry and Physiology of Polyamines in Plants

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Author

Hector E. Flores

ISBN #

0849368650

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Hector P Flores from Colorado Springs, CO, age ~69 Get Report