Harry Sue Phones & Addresses
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Wilmette, IL
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112 Red River Ct, Naperville, IL 60565 (630) 416-0092 (630) 416-3035
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Chicago, IL
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112 Red River Ct, Naperville, IL 60565 (630) 750-9513
Work
Position:
Service Occupations
Education
Degree:
High school graduate or higher
Emails
b***y@yahoo.com
Publications
Us Patents
Method For Manufacturing An Integrated Circuit Device
View pageUS Patent:
44855532, Dec 4, 1984
Filed:
Jun 27, 1983
Appl. No.:
6/508314
Inventors:
Raymond R. Christian - Oaklawn IL
Harry Sue - Chicago IL
Herbert A. Waggener - Lincolnshire IL
Joseph C. Zuercher - Wilmette IL
Harry Sue - Chicago IL
Herbert A. Waggener - Lincolnshire IL
Joseph C. Zuercher - Wilmette IL
Assignee:
Teletype Corporation - Skokie IL
International Classification:
H01L 2178
H01L 2195
H01L 2195
US Classification:
29589
Abstract:
An integrated circuit 14 having an active circuit 19 is formed on a circuit wafer 10. A moat 18 in the field oxide 20 surrounds the active circuit 19. Metallic conductor 30 passes from a location on the active circuit 19 over the moat 18 to a contact area 22. The wafer 10 is covered with a photoshaped silicon nitride layer 18, and a support wafer 40 is secured with adhesive 46 to the circuit side of the circuit wafer 10. The circuit wafer 10 is photoshaped to expose the metallic conductor 30 at the contact area 22, and the contact area 22 is prepared with multiple metal layers 62, 66, 70 for connection to external wiring.
Method For Manufacturing An Integrated Circuit Device
View pageUS Patent:
44728751, Sep 25, 1984
Filed:
Jun 27, 1983
Appl. No.:
6/508316
Inventors:
Raymond R. Christian - Oaklawn IL
Harry Sue - Chicago IL
Joseph C. Zuercher - Wilmette IL
Harry Sue - Chicago IL
Joseph C. Zuercher - Wilmette IL
Assignee:
Teletype Corporation - Skokie IL
International Classification:
H01L 2178
H01L 2195
H01L 2195
US Classification:
29577C
Abstract:
A method for manufacturing an integrated circuit thermal print head is illustrated including transistor 20 and a resistor doped region 22 formed on a first surface of a silicon circuit wafer 10. A contamination barrier in the form of a moat 26 filled with silicon nitride 30 is formed around the transistor 20. A support wafer 50 is secured to the first surface of the circuit wafer 10 by an adhesive layer 58. The circuit wafer 10 is thinned, and the exposed surface of the circuit wafer 10 is photoshaped to define wafer segments 68 positioned over the resistor doped region 22.
Starting Product For The Production Of A Read-Only Memory And A Method Of Producing It And The Read-Only Memory
View pageUS Patent:
40453103, Aug 30, 1977
Filed:
May 3, 1976
Appl. No.:
5/682411
Inventors:
Robert K. Jones - Centerville OH
Harry Sue - Chicago IL
Harry Sue - Chicago IL
Assignee:
Teletype Corporation - Skokie IL
International Classification:
C25F 300
C25F 314
C25F 314
US Classification:
2041294
Abstract:
A read-only memory is manufactured from a matrix or array of multilayer electrical devices, each of which includes at least one metallic layer, a portion of which contacts a doped semi conductor region. The metallic layers are controllably and rapidly thinned down and decreased in cross-sectional area in the vicinity of the doped regions to form fusible links, thus producing a ROM starting product. Fusible link formation is enhanced by the use of an etchant for the metallic layer which forms an electrochemical cell in conjunction therewith and with the semiconductor and the doped region. Any metallic layers not contacting a doped region are also etched by the etchant, but at the much slower "chemical rate". Following the production of the starting product, a ROM may be produced by the selective application of voltages to selected fusible links, the I. sup. 2 R heating of the links fusing them, or blowing them out.