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Harmeet S Sobti

from San Diego, CA
Age ~53
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Also known as:
Harmeet Sobti Singh, Harmeet Sotti
Phone and address:
7822 Chadamy Way, San Diego, CA 92130
Related to:
Pooja S Sobti, 46Kimberly Bobeck, 59Richard W Bobeck, 60Frank R Menardi, 92Priya E Sobti, 28Emma Bobeck, 30Helga A Menardi, 86Kimberly Bobeck, 53Robert W BobeckVirginia N Bobeck, 88Christine Menardi, 56Kimberley Menardi, 53Emma J BobeckFrank R Menardi, 50Stacey A Bobeck, 57
Connected to:
Anjeet K Sobti, 57Jasleen B Sobti, 56Neeraj Sobti, 56Jim P Sobtzak, 45Segun Sobulo, 45Joel B Soburn, 80Elizabeth J Sobus, 85Kate E Sobus, 35Laura A Sobus, 33Richard J Sobus, 40

Harmeet Sobti Phones & Addresses

  • 7822 Chadamy Way, San Diego, CA 92130
  • 15819 Graf St, Portland, OR 97229
  • Aloha, OR
  • Sunnyvale, CA
  • 1800 Creedmoor Ave, Pittsburgh, PA 15226
  • Orange, CA
  • Boynton Beach, FL

Resumes

Resumes

Harmeet Sobti Photo 1

Principal Engineer Dfm And Dfy

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Location:
San Diego, CA
Industry:
Semiconductors
Work:
Qualcomm
Principal Engineer Dfm and Dfy
Maxim Integrated 2003 - Oct 2012
Director, Product Engineering
Maxim Integrated 1999 - 2003
Manager, Product Engineering
Maxim Integrated 1995 - 1999
Member of Technical Staff
Education:
University of Southern California 1993 - 1994
Masters, Master of Science In Electrical Engineering, Electrical Engineering, Physics, Design Punjab Engineering College 1989 - 1993
Bachelors, Bachelor of Science In Electrical Engineering, Communication, Electronics
Skills:
Product Engineering
Device Physics
Electrical Engineering
Yield Enhancement
Analog Design
Failure Analysis
Semiconductors
Semiconductor Manufacturing
Analog
Analog Circuit Design
Bicmos
Cmos
Ic
Device Characterization
Power Management
Yield
Physics
Asic
Mixed Signal
Rf
Languages:
Punjabi
Hindi
Harmeet Sobti Photo 2

Director, Product Engineering At Maxim Integrated Products

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Location:
Portland, OR
Industry:
Semiconductors
Work:
Maxim Integrated
Director, Product Engineering at Maxim Integrated Products

Publications

Us Patents

Dual-Gate Vdmos Device

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US Patent:
20130082321, Apr 4, 2013
Filed:
Sep 30, 2011
Appl. No.:
13/249594
Inventors:
Harmeet Sobti - Portland OR, US
Timothy K. McGuire - Beaverton OR, US
David L. Snyder - Beaverton OR, US
Scott J. Alberhasky - Portland OR, US
Assignee:
Maxim Integrated Products, Inc. - Sunnyvale CA
International Classification:
H01L 29/78
H01L 21/336
US Classification:
257329, 438268, 257E29262, 257E2141
Abstract:
Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance.
Control profile
Harmeet S Sobti from San Diego, CA, age ~53 Get Report