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Harinath B Kamepalli

from San Jose, CA
Age ~46
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Also known as:
Harinath Babu Kamepalli, Harinath C Kamepalli
Phone and address:
1193 Thornbury Ln, San Jose, CA 95138
(408) 375-4274
Related to:
Kumari Kusuma Kusuma, 50Venky VaddineniDasaratha Bathala
Connected to:
Anne J Kamer, 66Bethany L Kamer, 54Christopher E Kamer, 56Debbie Kamer, 69Donna K Kamer, 49George V Kamer, 63Joseph W Kamer, 41Joshua Kamer, 38Stacy M Kamer, 45Deborah J Kamerer, 71

Harinath Kamepalli Phones & Addresses

  • 1193 Thornbury Ln, San Jose, CA 95138 (408) 375-4274
  • Sunnyvale, CA
  • Mountain View, CA
  • 901 San Antonio Rd, Palo Alto, CA 94303
  • 414 7Th St, Minneapolis, MN 55414 (651) 617-9725
  • Chelmsford, MA
  • 1193 Thornbury Ln, San Jose, CA 95138

Work

Company: Synopsys inc. Apr 2010 Position: Sr. manager

Education

Degree: MS School / High School: Stanford University 2005 to 2006 Specialities: Management Science and Engineering

Skills

Machine Learning • Neural Networks • Deep Learning • High Performance Computing • C++ • Python • Fpga • Gpu • C • Cuda • Openmp • Opencl • Emulation • Project Management • Agile Project Management • Algorithms • Software Engineering • Perl • Shell Scripting • Eda • Verilog • Asic • Soc • Hardware Architecture • Rtl Design • Formal Verification • Functional Verification • Debugging • Computer Architecture • Post Merger Team Integration • Mergers and Acquisitions • Test Driven Development

Languages

English • Telugu • Hindi

Ranks

Certificate: Machine Learning

Interests

Children

Industries

Computer Software

Resumes

Resumes

Harinath Kamepalli Photo 1

Senior Director Of Software

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Location:
San Francisco, CA
Industry:
Computer Software
Work:
Synopsys Inc. since Apr 2010
Sr. Manager
ZeroSoft, Inc. Dec 2007 - Mar 2010
Vice President of Products
Atheros Communications Oct 2006 - Nov 2007
Digital Verification Architect
Sun Microsystems Feb 2001 - Sep 2006
Sr Engineer
Sun Microsystems May 2000 - Aug 2000
Graduate Intern
Education:
Stanford University 2005 - 2006
MS, Management Science and Engineering University of Minnesota Sep 1999 - Dec 2000
MS, Electrical Engineering National Institute of Technology Warangal 1995 - 1999
B.Tech, Electrical and Electronics Engineering
Skills:
Machine Learning
Neural Networks
Deep Learning
High Performance Computing
C++
Python
Fpga
Gpu
C
Cuda
Openmp
Opencl
Emulation
Project Management
Agile Project Management
Algorithms
Software Engineering
Perl
Shell Scripting
Eda
Verilog
Asic
Soc
Hardware Architecture
Rtl Design
Formal Verification
Functional Verification
Debugging
Computer Architecture
Post Merger Team Integration
Mergers and Acquisitions
Test Driven Development
Interests:
Children
Languages:
English
Telugu
Hindi
Certifications:
Machine Learning
Neural Networks For Machine Learning
Deep Learning Specialization

Publications

Us Patents

Scan Chain Verification Using Symbolic Simulation

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US Patent:
7055118, May 30, 2006
Filed:
Mar 1, 2004
Appl. No.:
10/790650
Inventors:
Harinath B. Kamepalli - Mountain View CA, US
Padmaraj Sanjeevarao - Sunnyvale CA, US
Chang-Jin Park - Cupertino CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 17/50
US Classification:
716 5, 716 18
Abstract:
A method and apparatus for improved formal scan chain equivalence checking to verify the operation of components in a VLSI integrated circuit is described in connection with using symbolic simulation for verification of scan chain equivalency between different modeling representations of a circuit-under-test. The present invention enhances previous techniques by loading each scannable state-element in the circuit design with a symbolic expression that characterizes the logical location of the element and performing a scan shift operation to verify the contents of each scannable state-element at the scan-out and other primary output pins of the design.
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Harinath B Kamepalli from San Jose, CA, age ~46 Get Report