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Haoxing Ren

from Round Rock, TX
Age ~48
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Also known as:
Ren Haoxing, G Ren
Related to:
Qi RenGaofeng Ren, 76
Connected to:
Chao Ren, 61Charles R Ren, 62Cheng J Ren, 42Chenghui Ren, 68Christopher F Ren, 56Ci Ren, 34Daihong Ren, 58Daxin X Ren, 80Emma V Ren, 64Frances M Ren, 82

Haoxing Ren Phones & Addresses

  • Round Rock, TX
    • s
  • 9905 Ivalenes Hope Dr, Austin, TX 78717
  • Wappingers Falls, NY

Work

Company: Chinese american semiconductor professional association (caspa) Apr 2013 Address: Austin, Texas Area Position: Director, board of austin chapter

Education

Degree: PhD School / High School: The University of Texas at Austin 2003 to 2006 Specialities: Computer Engineering

Skills

Microprocessors • Physical Design • High Level Synthesis • Asic • Static Timing Analysis • Computer Architecture • Vlsi • Verilog • Algorithms • Eda • C++ • Logic Synthesis • Debugging • Tcl • Physical Synthesis • Perl

Languages

Mandarin • English

Awards

Ieee cas region 1-7 chapter of the year ... • Ibm outstanding technical achievement aw... • Ibm research outstanding technical accom... • Ibm research technical accomplishment aw... • Ibm research technical accomplishment aw... • Ibm research outstanding technical accom... • Best paper award of international sympos...

Industries

Research

Resumes

Resumes

Haoxing Ren Photo 1

Haoxing Ren

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Location:
9520 Indina Hills Dr, Austin, TX 78717
Industry:
Research
Work:
Chinese American Semiconductor Professional Association (CASPA) - Austin, Texas Area since Apr 2013
Director, Board of Austin Chapter
IBM T. J. Watson Research Center since 2007
Research Staff Member
IEEE 2009 - 2011
Chair of Central Texas SSC/CAS Joint Chapter
IBM Jun 2006 - Jan 2007
Advisory Software Engineer
IBM Aug 2000 - Jun 2006
Staff Software Engineer
Education:
The University of Texas at Austin 2003 - 2006
PhD, Computer Engineering Rensselaer Polytechnic Institute 1999 - 2000
Master's degree, computer engineering Shanghai Jiao Tong University 1992 - 1999
BS, MS, Electrical Engineering
Skills:
Microprocessors
Physical Design
High Level Synthesis
Asic
Static Timing Analysis
Computer Architecture
Vlsi
Verilog
Algorithms
Eda
C++
Logic Synthesis
Debugging
Tcl
Physical Synthesis
Perl
Languages:
Mandarin
English
Awards:
IEEE CAS Region 1-7 Chapter of the Year Award
IEEE Circuits and Systems Society
The Regions 1-7 Chapter of the Year Award recognizes the Chapter in regions 1-7 with the very best yearly activities. The award is based on number and quality of chapter activities, percentage of members attending sponsored events, membership development activities and chapter growth, local conferences/symposia/workshops, participation in the Distinguished Lecturer Program, involvement of students and GOLD members and timelines of reporting. The overall local environment and factors such as chapter size are also considered. http://ieee-cas.org/about/awards/regions-1-7-chapter-of-the-year-award
IBM Outstanding Technical Achievement Award
IBM
IBM Outstanding Technical Achievement Award for “Contribution to Design Closure: PDSRTL and PDS-PLATO”
IBM Research Outstanding Technical Accomplishment Award
IBM
IBM Research Outstanding Technical Accomplishment Award for “Large Block Synthesis and Structured Synthesis for Server Design Productivity”, 2009
IBM Research Technical Accomplishment Award
IBM
IBM Research Technical Accomplishment Award for “Incremental Synthesis for Engineering Changes for IBM Servers, Gaming Microprocessor and System ASIC Chips”
IBM Research Technical Accomplishment Award
IBM
IBM Research Technical Accomplishment Award for “Tools and Design Assistance in Benchmarking Effort to Win a Major ASIC Bid"
IBM Research Outstanding Technical Accomplishment
IBM
Incremental Synthesis for Engineering Changes for IBM Servers
Best Paper Award of International Symposium on Physical Design
IEEE SIGDA
"Network Flow Based Datapath Bit Slicing" : a datapath physical synthesis paper

Business Records

Name / Title
Company / Classification
Phones & Addresses
Haoxing Ren
Director
JTU ALUMNI ASSOICATION OF AUSTIN
Civic/Social Association
10641 Bramblecrest Dr, Austin, TX 78726

Publications

Us Patents

Method And Apparatus For Diffusion Based Cell Placement Migration

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US Patent:
7464356, Dec 9, 2008
Filed:
Dec 15, 2005
Appl. No.:
11/304955
Inventors:
Charles Jay Alpert - Cedar Park TX, US
Haoxing Ren - Austin TX, US
Paul Gerard Villarrubia - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 8, 716 9, 716 10, 716 11, 716 12, 716 13, 716 14
Abstract:
A method for cell placement in an integrated circuit design that uses a calculated diffusion velocity determined from a density value in order to relocate the cells until the cell placement reduces the density below a predetermined threshold. The method acts to control the movement of different cells to reduce the density of the cells prior to legalization of the cell placement.

Constrained Detailed Placement

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US Patent:
7467369, Dec 16, 2008
Filed:
Oct 30, 2006
Appl. No.:
11/554235
Inventors:
Charles J. Alpert - Cedar Park TX, US
Gi-Joon Nam - Austin TX, US
Haoxing Ren - Austin TX, US
Paul G. Villarrubia - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
G06F 9/45
US Classification:
716 9, 716 8, 716 10, 716 11
Abstract:
The illustrative embodiments provide a computer implemented method which perform cell transforms that decrease overall wire length, without degrading device timing or violating electrical constraints. The process computes delay constraint coefficients for a data set. The process performs a detailed placement transform by moving a subset of cells, making the placement legal, computing a half perimeter wire length change for each output net that is a member of the subset of nets, and computing a Manhattan distance change for each source-sink gate pair within the move cells. the process computes a weighted total wire length incremented value for the transformed data set. Further, the process continues by evaluating arrival time constraints, electrical constraints, and user configurable move limits for violations, and restoring the move cells to the original placement if a violation is found.

Flow Based Package Pin Assignment

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US Patent:
7533360, May 12, 2009
Filed:
Jul 22, 2008
Appl. No.:
12/177648
Inventors:
Haoxing Ren - Austin TX, US
Hua Xiang - Yorktown Heights NY, US
Tingdong Zhou - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 12
Abstract:
The present invention provides a method of performing BSM assignments for each routing layer typically having one BSM group (e. g. memory bus) per layer. Further, the present invention provides for routable BSM assignments. Further, the present invention provides a method for handling pair constraints providing for differential pairs to be placed close to each other. Further, the method of the present invention provides for simultaneous routing and pin assignments while honoring pair constraint concerns and optimizing wire length.

Clock Aware Placement

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US Patent:
7624366, Nov 24, 2009
Filed:
Oct 31, 2006
Appl. No.:
11/554637
Inventors:
Charles J. Alpert - Cedar Park TX, US
David J. Hathaway - Underhill VT, US
William R. Migatz - Wappingers Falls NY, US
Gi-Joon Nam - Austin TX, US
Haoxing Ren - Austin TX, US
Paul G. Villarrubia - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 10
Abstract:
The layout of latches in a common clock domain is efficiently optimized to shrink the physical size of the domain while maintaining timing requirements. The latches are placed in a first layout preferably using quadratic placement, and a star object is built representing an interim clock structure. The latches are weighted based on wire distance from a source of the star object, and then re-placed using the weighting. The weighted placement and repartitioning may be iteratively repeated until a target number of bins is reached. The boundary of the latches in the final global placement is used to define a movebound for further detailed placement.

Apparatus And Method For Improved Test Controllability And Observability Of Random Resistant Logic

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US Patent:
7882454, Feb 1, 2011
Filed:
Apr 28, 2008
Appl. No.:
12/110731
Inventors:
Mary P Kusko - Hopewell Junction NY, US
Haoxing Ren - Austin TX, US
Ronald G Walther - Austin TX, US
Rona Yaari - New York NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 1
Abstract:
A method for implementing improved observability of random resistant logic included in an integrated circuit (IC) design includes configuring a multiplexer device to pass, to a preexisting storage latch within the design, one of: a signal from one or more observation points within the random resistant logic and an output of first preexisting combinational logic; and selecting a preexisting net within the IC design to generate a randomized logic signal that, in a test mode, is passed to the multiplexer device to serve as a control signal thereto; wherein, in the test mode, the existing storage latch captures data randomly selected from either the existing combinational logic and the one or more observation points and in a normal mode, the existing storage latch captures data from only the existing combinational logic, facilitating random testing of the random resistant logic in a manner that avoids adding latches to the design.

Method To Reduce The Wirelength Of Analytical Placement Techniques By Modulation Of Spreading Forces Vectors

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US Patent:
7882475, Feb 1, 2011
Filed:
Jul 29, 2008
Appl. No.:
12/181447
Inventors:
Charles J. Alpert - Cedar Park TX, US
Gi-Joon Nam - Austin TX, US
Haoxing Ren - Austin TX, US
Paul G. Villarrubia - Austin TX, US
Natarajan Viswanathan - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
G06F 9/45
US Classification:
716 8, 716 9, 716 10, 716 11, 716 12
Abstract:
A method of force directed placement programming is presented. The method includes: assigning a plurality of objects from a cell netlist to bins; shifting the objects based on the bins; computing a magnitude of a spreading force for each object of the plurality of objects based on the shifting; sorting the objects based on the magnitude of the spreading force of the objects; selecting a subset of the sorted objects based on a threshold value indicating at least one of a top percentage, a threshold force, and a threshold value that is based on a placement congestion; adjusting the spreading force of the selected objects to be equal to a predetermined value indicating a minimum spreading force; and determining a placement of the objects based on adjusted spreading force of the selected objects.

System And Computer Program Product For Diffusion Based Cell Placement Migration

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US Patent:
8112732, Feb 7, 2012
Filed:
Nov 4, 2008
Appl. No.:
12/264619
Inventors:
Charles J Alpert - Cedar Park TX, US
Haoxing Ren - Austin TX, US
Paul Gerard Villarubia - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716119, 716107, 716108, 716109, 716118, 716123, 716125, 716126, 716132, 716136, 716139
Abstract:
A system and computer program product for cell placement in an integrated circuit design that uses a calculated diffusion velocity determined from a density value in order to relocate the cells until the cell placement reduces the density below a predetermined threshold. The method acts to control the movement of different cells to reduce the density of the cells prior to legalization of the cell placement.

Logic Difference Synthesis

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US Patent:
8122400, Feb 21, 2012
Filed:
Jul 2, 2009
Appl. No.:
12/497499
Inventors:
Jeremy T. Hopkins - Round Rock TX, US
John M. Isakson - Austin TX, US
Joachim Keinert - Altdorf, DE
Smita Krishnaswamy - New York NY, US
Nilesh A. Modi - Santa Barbara CA, US
Ruchir Puri - Baldwin Place NY, US
Haoxing Ren - Austin TX, US
David L. Rude - Wendell NC, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716104, 716100, 716101, 716106, 716107
Abstract:
A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original circuit. The synthesis may locate an output-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the output-side boundary and the primary output elements of the original circuit. The disclosed synthesis may also locate an input-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the input-side boundary and the primary input elements of the original circuit. A computer program products are also disclosed. The computer program product contains a computer useable medium having a computer readable program code embodied therein.
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Haoxing Ren from Round Rock, TX, age ~48 Get Report