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Guy Edward Mcswain

from Cypress, TX
Age ~67
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Also known as:
Guy E Mcswain, Guy Mc Swain, Guy Mc
Phone and address:
13214 Golden Valley Dr, Cypress, TX 77429
(281) 320-9824
Related to:
Claire C Mcswain, 32
Connected to:
Alex Mcswain, 36Arnette D Mcswain, 51Autumn Mcswain, 61Blake W Mcswain, 35Darry J Mcswain, 66Elias Mcswain, 50Garrett A Mcswain, 50George Mcswain, 53Jarae Mcswain, 38Jeremiah Mcswain, 32

Guy Mcswain Phones & Addresses

  • 13214 Golden Valley Dr, Cypress, TX 77429 (281) 320-9824
  • Houston, TX
  • Tomball, TX
  • 13214 Golden Valley Dr, Cypress, TX 77429 (281) 851-8716

Work

Company: Hewlett-packard Aug 1986 to 2000 Position: Asic design manager and platform program manager

Education

Degree: Bachelors, Bachelor of Arts School / High School: The University of Texas at Austin 1979 to 1980 Specialities: Computer Science

Skills

Embedded Systems • Asic • Cloud Computing • Virtualization • Hardware • Data Center • Perl • Software Development • Computer Hardware • Storage • Agile Methodologies • Dram • Supplier Quality Engineering • Seismic Data Aquisition

Languages

French

Industries

Computer Hardware

Resumes

Resumes

Guy Mcswain Photo 1

Director Of Engineering, Bladesystems And Memory

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Location:
Cypress, TX
Industry:
Computer Hardware
Work:
Hewlett-Packard Aug 1986 - 2000
Asic Design Manager and Platform Program Manager
Hewlett-Packard Aug 1986 - 2000
Director of Engineering, Bladesystems and Memory
Western Geophysical Oct 1981 - Aug 1986
Design Engineer
Education:
The University of Texas at Austin 1979 - 1980
Bachelors, Bachelor of Arts, Computer Science
Skills:
Embedded Systems
Asic
Cloud Computing
Virtualization
Hardware
Data Center
Perl
Software Development
Computer Hardware
Storage
Agile Methodologies
Dram
Supplier Quality Engineering
Seismic Data Aquisition
Languages:
French

Publications

Us Patents

Self-Orienting Logo Assembly

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US Patent:
6477799, Nov 12, 2002
Filed:
Mar 13, 2000
Appl. No.:
09/523858
Inventors:
Carol Erickson - Cypress TX
Kenneth Jansen - Spring TX
David R. Wooten - Escondido TX
Guy McSwain - Cypress TX
Michael F. Angelo - Houston TX
Keith Lutsch - Houston TX
Assignee:
Compaq Information Technologies Group, L.P. - Houston TX
International Classification:
G09F 1900
US Classification:
40406, 40409, 40422, 40426, 4066101, 446267
Abstract:
A self-orienting logo assembly so that the logo is always in a horizontal orientation. In the preferred embodiments the logo is located on a disk. The disk is weighted or otherwise designed to have its weight distributed nonuniformly. The disk is located inside a housing. The housing is attached to the computer or other equipment bearing the logo. When the housing is located in a vertical plane the disk rotates to allow the logo to remain horizontal. The disk can be rotationally mounted to the housing or can be suspended in liquid. In an alternate embodiment the disk can have a magnet incorporated so that when the disk is in a horizontal orientation it can act as a compass. In another embodiment a portion of the disk is removed and the housing contains an additional logo or wording. The rotation of the disk can then cover or expose the additional logo or wording.

Arrangement Of Dma, Interrupt And Timer Functions To Implement Symmetrical Processing In A Multiprocessor Computer System

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US Patent:
54370426, Jul 25, 1995
Filed:
Oct 2, 1992
Appl. No.:
7/955683
Inventors:
Paul R. Culley - Cypress TX
John A. Landry - Tomball TX
Dale J. Mayer - Houston TX
Christopher C. Wanner - Houston TX
Guy E. McSwain - Cypress TX
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
G06F 1300
US Classification:
395800
Abstract:
An arrangement of direct memory access (DMA), interrupt and timer functions in a multiprocessor computer system to allow symmetrical processing. Several functions which are considered common to all of the CPUs and those which are conveniently accessed through an expansion bus remain in a central system peripheral chip coupled to the expansion bus. These central functions include the primary portions of the DMA controller and arbitration circuitry to control access of the expansion bus. A distributed peripheral, including a programmable interrupt controller, multiprocessor interrupt logic, nonmaskable interrupt logic, local DMA logic and timer functions, is provided locally for each CPU. A bus is provided between the central and distributed peripherals to allow the central peripheral to broadcast information to the CPUs, and to provide local information from the distributed chip to the central peripheral when the local CPU is programming or accessing functions in the central peripheral.

Cache Memory Using Unique Burst Counter Circuitry And Asynchronous Interleaved Ram Banks For Zero Wait State Operation

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US Patent:
57936935, Aug 11, 1998
Filed:
Nov 4, 1996
Appl. No.:
8/743501
Inventors:
Michael J. Collins - Tomball TX
Jeffrey C. Stevens - Spring TX
Guy E. McSwain - Cypress TX
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
G11C 1300
US Classification:
36523001
Abstract:
A cache memory system utilizing asynchronous/synchronous burst counter circuitry which lessens the need for expensive, high speed data SRAM to achieve zero wait-state operation. The burst counter circuitry takes advantage of the fact that a read address is present on the address bus approximately one-halfway through the initial bus cycle (T1) during a burst read. Unlike synchronous prior art burst counters, burst counter circuitry according to the invention is configured to forward the address to asynchronous address decoders as soon as it is present, rather than waiting for the next rising edge of the processor clock. For accesses to the first cache line, the timing budget therefore includes the first complete clock cycle of a burst read (T2) plus an extra half-clock cycle from T1. The extra time is utilized to retrieve data from the data SRAM core for provision to the processor data bus at the end of the bus cycle T2. Subsequent accesses are controlled by the burst counter in a synchronous fashion that corresponds to a processor specific burst ordering scheme.

Repairing A Memory Device

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US Patent:
20150227461, Aug 13, 2015
Filed:
Oct 31, 2012
Appl. No.:
14/425247
Inventors:
- Houston TX, US
Eric L. Pope - Houston TX, US
Reza M. Bacchus - Houston TX, US
Guy E. McSwain - Houston TX, US
Joseph W. Fahy - Houston TX, US
International Classification:
G06F 12/06
Abstract:
A technique includes during in-service use of a memory package in a computer system, using a first interface to access a defective address memory of the memory package. The defective address memory is accessible by a manufacturer of the memory package prior to the in-service use using a second interface of the memory package other than the first interface. In connection with the in-service use of the memory package, the memory package is repair, a repair that includes storing a defective address in the defective address memory to change an address mapping for at least one cell of the storage array.

Apparatus And Method For Selecting Memory Outside A Memory Array

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US Patent:
20150095564, Apr 2, 2015
Filed:
May 9, 2012
Appl. No.:
14/396600
Inventors:
Melvin K. Benedict - Magnolia TX, US
Eric L. Pope - Tomball TX, US
Guy E. McSwain - Cypress TX, US
Joseph W. Fahy - Houston TX, US
Maurizio Contini - Belmont MA, US
International Classification:
G11C 7/10
G11C 11/406
US Classification:
711105
Abstract:
An apparatus includes a memory module, which includes a memory array. The memory array includes rows of memory and columns of memory. The apparatus also includes at least one row of memory not in the memory array and a register. The register includes an address space and a row/column indicator. The apparatus also includes row selection logic to select the at least one row to be activated if the address from an address bus equals the register value and if the row/column indicator indicates row.
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Guy Edward Mcswain from Cypress, TX, age ~67 Get Report