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Gus P Ikonomopoulos

from Lakeway, TX
Age ~52
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Also known as:
Gus Peter Ikonomopoulos, Gus P Ikonomopoulo, Gus S
Phone and address:
110 Knarr St, Austin, TX 78734
(512) 261-5410
Related to:
Nikki P Ikonomopoulos, 49Bradley D Kieffer, 47James P Ikonomopoulos, 40Kristi J Akin, 67Karen M Ikonomopoulos, 52Peter K Ikonomopoulos, 81Christina P Ikonomopoulos, 77Panagiotis Ikonomopoulos, 81Peter Ikonomopoulos, 79Donald E Kieffer, 52L KiefferDean J Kieffer, 45
Connected to:
Georgi P Ikonomov, 41Marcia I Ikonomopoulos, 79Metodi L Ikonomov, 61Ekaete K Ikott, 43Anthony N Ikpa, 38Matthew Ikpa, 33Samuel I Ikpe, 41Jesam Ikpi, 46Letitia A Ikpo, 52Adam Ikram, 39

Gus Ikonomopoulos Phones & Addresses

  • 110 Knarr St, Lakeway, TX 78734 (512) 261-5410
  • 243 Mooring Cir, Lakeway, TX 78734 (512) 261-5410
  • Austin, TX
  • Mount Carmel, IL
  • Cary, IL
  • Champaign, IL

Resumes

Resumes

Gus Ikonomopoulos Photo 1

Gpu Logic Design Engineer

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Location:
Austin, TX
Industry:
Semiconductors
Work:
Apple
Gpu Logic Design Engineer
Education:
University of Illinois at Urbana - Champaign 1990 - 1994
Bachelors, Bachelor of Science
Skills:
Rtl Design
Microarchitecture
Verilog
Rtl Verification
C++
C
Perl
Silicon Validation
Laboratory Skills
Soldering
Gus Ikonomopoulos Photo 2

Gus Ikonomopoulos

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Location:
Austin, TX
Industry:
Computer Hardware

Publications

Us Patents

Parallel Error Checking For Multiple Packets

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US Patent:
20030233609, Dec 18, 2003
Filed:
Jun 18, 2002
Appl. No.:
10/173757
Inventors:
Gus Ikonomopoulos - Austin TX, US
Srinath Audityan - Austin TX, US
International Classification:
H03M013/00
US Classification:
714/758000
Abstract:
Portions of error checking circuitry (-) are replicated so that the accumulated information () which is error checked in parallel may include any number of packets boundaries at any location. The location of packet boundaries, which may be information provided from system interconnect for a receiver, is used to control routing (e.g. MUXes ) and the selection of one or more final checksum(s) (-). In one embodiment, CRC checker circuitry () uses multiple XOR trees (-) along with a system of controlled routing multiplexers () and final_checksum select logic () to perform error checking on accumulated information which may include any number of packets boundaries at any location.

Method Of Monitoring Timeout Conditions And Device Therefor

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US Patent:
20060277447, Dec 7, 2006
Filed:
Jun 1, 2005
Appl. No.:
11/142639
Inventors:
Harold Martin - Austin TX, US
Thang Nguyen - Austin TX, US
Gus Ikonomopoulos - Lakeway TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G06F 11/00
US Classification:
714055000
Abstract:
A maximum timeout time for a communication between devices is determined. A time period is determined for a plurality of time zones based upon the maximum timeout time. A current time zone is updated every time period. A timeout zone for an outstanding transaction is associated with a first time zone to indicate when the outstanding transaction will timeout if not completed. In one embodiment, the time period for each time zone is approximately equal to the maximum timeout period divided by a predetermined number of time zones, which may be the total number of time zones, e.g. eight or sixteen.

Interconnect Controller For A Data Processing Device And Method Therefor

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US Patent:
20110107065, May 5, 2011
Filed:
Oct 29, 2009
Appl. No.:
12/608525
Inventors:
Gus P. Ikonomopoulos - Lakeway TX, US
Thang Q. Nguyen - Austin TX, US
Jose M. Nunez - Austin TX, US
Kun Xu - Austin TX, US
Assignee:
FREESCALE SEMICONDUCTOR, INC. - Austin TX
International Classification:
G06F 9/30
US Classification:
712220, 712E09016
Abstract:
A data processing device includes an interconnect controller operable to manage the communication of information between modules of the data processing device via an interconnect. In response to a transaction request the interconnect controller selects a tag value from a set of available tag values, assigns the tag to the transaction and reserves the tag value so that it is unavailable for assignment to other transactions. If an expected response to the transaction request is not received within a designated amount of time, the transaction enters a timed-out state and the interconnect controller locks the tag value, so that it remains unavailable for assignment to other transactions until an unlock event, such as a request from software.

Read Stacking For Data Processor Interface

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US Patent:
20120226841, Sep 6, 2012
Filed:
Mar 1, 2011
Appl. No.:
13/038054
Inventors:
Thang Q. Nguyen - Austin TX, US
Gus P. Ikonomopoulos - Lakeway TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G06F 13/20
US Classification:
710112
Abstract:
A gasket of a data processing device controls the number of released storage locations of a buffer where read and write access requests are stored so that more read access requests can be stored without a corresponding increase in the amount of space at the buffer to store write access requests. An interface of the gasket accepts new access requests from one or more requesting modules only when a number of released storage locations at a buffer associated with the interface (referred to as an outbound buffer) is above a threshold number. As long as the number of stored access requests at the outbound buffer are less than a threshold amount, a buffer location can be immediately released. In addition, the gasket is configured to issue read access requests from the outbound buffer without regard to whether the inbound buffer has space available.

Method For Reordering Out Of Order Responses From Decomposed Requests In Bridge Ip

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US Patent:
20190220423, Jul 18, 2019
Filed:
Jan 18, 2018
Appl. No.:
15/874175
Inventors:
- Austin TX, US
Gus P. Ikonomopoulos - Lakeway TX, US
Assignee:
NXP USA, Inc. - Austin TX
International Classification:
G06F 13/16
G06F 13/42
G06F 13/364
Abstract:
Upon receiving a request () in an initiator interface protocol identifying information to be returned in-order, an integrated circuit protocol bridge circuit device () allocates, to the ordered request, entries in a first ordered queue (e.g., ) and a first static queue (e.g., ) for the initiator interface protocol, generates a plurality of split target requests in a target interface protocol from the ordered request, and allocates the plurality of split target requests to entries in a second ordered queue (e.g., ) and a second static queue (e.g., ) for the target interface protocol, so that, upon receiving a plurality of out-of-order target responses, an allocated entry in the first ordered queue () for the first ordered initiator request is deleted only after a plurality of counter fields in the first static queue indicate that target responses have been received for all of the plurality of split target requests.

Direct Memory Access (Dma) Unit With Address Alignment

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US Patent:
20180004692, Jan 4, 2018
Filed:
Jun 29, 2016
Appl. No.:
15/197229
Inventors:
- Austin TX, US
GUS IKONOMOPOULOS - Austin TX, US
JATIN VINAY PAI - Austin TX, US
International Classification:
G06F 13/28
G06F 13/40
G06F 13/16
Abstract:
Systems and methods for operating a DMA unit with address alignment are disclosed. These may include configuring a bandwidth control setting for a read job that includes a data transfer size corresponding to a first number of bytes. A second number of bytes to reach a read address alignment is determined. In a first data transfer, a third number of bytes substantially equal to the first number of bytes plus the second number of bytes are transferred. In subsequent data transfers of the read job, the first number of bytes are transferred to the data buffer. After the third number of bytes are transferred to the data buffer, a fourth number of bytes from the data buffer are transferred to a destination.
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Gus P Ikonomopoulos from Lakeway, TX, age ~52 Get Report