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Guanhao P Shen

from Austin, TX
Age ~45
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Connected to:
Aileen C Shen, 41Audrey S Shen, 88Bai Shen, 41Bao Z Shen, 74Beiyi Shen, 44Bella M Shen, 75Beverly G Shen, 41Billy Shen, 82Bingxin Shen, 41Caroline Shen, 74

Guanhao Shen Phones & Addresses

    s
  • 2717 Andrea Ridge Cv, Austin, TX 78738
  • Atlanta, GA

Resumes

Resumes

Guanhao Shen Photo 1

Member Of Technical Staff

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Location:
Austin, TX
Industry:
Semiconductors
Work:
Amd
Member of Technical Staff
Amd Jul 2012 - Jun 2015
Senior Design Engineer
Georgia Institute of Technology Jan 2012 - May 2012
Graduate Teaching Assistant
Georgia Institute of Technology Aug 2008 - Dec 2011
Graduate Research Assistant
Shanghai Ic Design Center Aug 2004 - Aug 2008
Design Engineer
Education:
Georgia Institute of Technology 2008 - 2012
Master of Science, Masters, Computer Science Tsinghua University 2002 - 2004
Bachelors, Bachelor of Science Nanjing University of Technology 1998 - 2002
Bachelors, Bachelor of Science, Computer Science
Skills:
Computer Architecture
Vlsi
Rtl Design
C
Microprocessors
Processors
C++
Static Timing Analysis
Verilog
Simulations
Hardware Design
Simulation
Asic
Perl
Cadence Virtuoso
Modelsim
Assembly
Ic
Semiconductors
Eda
Digital Design
Primetime
Physical Design
Timing Closure
Clock Tree Synthesis
Hercules
Floorplanning
Memory Design
Dram
Microarchitecture
Multi Core
Low Power Design
Astro
Low Power Design
Physical Verification
Functional Verification
Behavioral Modeling
3D Ic
Guanhao Shen Photo 2

Student At Georgia Institute Of Technology

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Location:
Greater Atlanta Area
Industry:
Computer Hardware

Publications

Us Patents

Dynamically Determining Memory Access Burst Length

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US Patent:
20190196996, Jun 27, 2019
Filed:
Dec 21, 2017
Appl. No.:
15/851087
Inventors:
- Sunnyvale CA, US
Ravindra N. Bhargava - Austin TX, US
Guanhao Shen - Austin TX, US
James Raymond Magro - Austin TX, US
Kevin M. Brandl - Austin TX, US
International Classification:
G06F 13/30
G06F 13/16
G06F 3/06
Abstract:
Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory read requests have been sent to a memory device in a read mode of a data bus, the memory controller determines a threshold number of memory write requests to send to the memory device in an upcoming write mode is a number of outstanding memory write requests. Alternatively, the memory controller determines the threshold number of memory write requests to send to the memory device in an upcoming write mode is a maximum value of the number of outstanding memory write requests and a programmable value of the write burst length stored in a control register. Therefore, the write burst length is determined dynamically. Similarly, the read burst length is determined dynamically when the write mode ends.

Memory Controller With Flexible Address Decoding

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US Patent:
20180019006, Jan 18, 2018
Filed:
Jul 15, 2016
Appl. No.:
15/211887
Inventors:
- Sunnyvale CA, US
Thomas Hamilton - Manor TX, US
Hideki Kanayama - San Jose CA, US
Kedarnath Balakrishnan - Austin TX, US
James R. Magro - Austin TX, US
Guanhao Shen - Austin TX, US
Mark Fowler - Hopkinton MA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G11C 7/10
G11C 11/408
Abstract:
A memory controller includes a host interface for receiving memory access requests including access addresses, a memory interface for providing memory accesses to a memory system, and an address decoder coupled to the host interface for programmably mapping the access addresses to selected ones of a plurality of regions. The address decoder is programmable to map the access addresses to a first region having a non-power-of-two size using a primary decoder and a secondary decoder each having power-of-two sizes, and providing a first region mapping signal in response. A command queue stores the memory access requests and region mapping signals. An arbiter picks the memory access requests from the command queue based on a plurality of criteria, which are evaluated based in part on the region mapping signals, and provides corresponding memory accesses to the memory interface in response.
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Guanhao P Shen from Austin, TX, age ~45 Get Report