Search

Gregory Uehara Phones & Addresses

  • Honolulu, HI
  • Pepeekeo, HI
  • Aiea, HI
  • Kapolei, HI
  • Waipahu, HI

Publications

Us Patents

Multiplexed Codec For An Adsl System

View page
US Patent:
6459684, Oct 1, 2002
Filed:
Feb 16, 1999
Appl. No.:
09/250426
Inventors:
Cormac S. Conroy - Sunnyvale CA
Samuel W. Sheng - Santa Clara CA
Gregory T. Uehara - Honolulu HI
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H04B 320
US Classification:
370286, 370494, 370208, 379410
Abstract:
An ADSL central office transmission system for transmitting downstream DMT signals to a plurality of remote ADSL transceiver is disclosed. The system includes a DMT digital signal transceiver that generates a time division multiplexed digital signal that includes a plurality of DMT signals to be sent on a plurality of ADSL lines. A digital to analog converter converts the time division multiplexed digital signal into a time division multiplexed analog signal that includes a plurality of analog DMT signals. The analog to digital converter has an output that outputs the time division multiplexed analog signal. A switch selectively connects the output of the digital to analog converter to each of a plurality of transmitters. The transmitters are configured to drive the plurality of ADSL lines. Thus, the plurality ADSL lines are driven by the plurality of analog DMT signals.

Frequency And Q-Factor Tunable Filters Using Frequency Translatable Impedance Structures

View page
US Patent:
20140044224, Feb 13, 2014
Filed:
Oct 22, 2013
Appl. No.:
14/060119
Inventors:
- St. Michael, BB
Gregory Uehara - Kaneohe HI, US
Sehat Sutardja - Los Altos Hills CA, US
Assignee:
Marvell World Trade Ltd. - St. Michael
International Classification:
H04B 1/10
US Classification:
375350
Abstract:
A system including a filter and a downconverter. The filter is configured to receive, from a node, (i) a first signal and (ii) a second signal, and filter the second signal. The filter includes a first input impedance. The filter comprises a first plurality of switches and a first circuit. The first plurality of switches is configured to communicate with the node. The first plurality of switches is clocked at a first frequency. The first frequency is based on a frequency of the first signal. The first circuit is configured to communicate with an output of the plurality of switches. The first circuit includes a second input impedance. The second input impedance is different than the first input impedance. The downconverter is configured to (i) receive the first signal and (ii) downconvert the first signal. The filter and the downconverter are connected in parallel to the node.

Digitally Calibrated Bandgap Reference

View page
US Patent:
62750984, Aug 14, 2001
Filed:
Oct 1, 1999
Appl. No.:
9/411342
Inventors:
Gregory T. Uehara - Honolulu HI
Samuel Sheng - San Jose CA
Cormac Conroy - Sunnyvale CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G05F 316
US Classification:
327539
Abstract:
A system and method for compensating for a voltage offset between an inverting input and a noninverting input of an op amp to provide a stable bandgap reference. The method including measuring the voltage offset between the inverting input and the noninverting input of the op amp and searching for a compensating current input to the op amp that compensates for the voltage offset. A programmable current source is set to output the compensating current to the op amp.

Spread-Spectrum Continous-Time Analog Correlator And Method Therefor

View page
US Patent:
63302748, Dec 11, 2001
Filed:
Sep 7, 1999
Appl. No.:
9/391117
Inventors:
Gregory T. Uehara - Honolulu HI
Assignee:
University of Hawaii - Honolulu HI
International Classification:
H04B 1707
US Classification:
375150
Abstract:
The present invention is a correlator for use in spread spectrum applications which utilizing continuous-time analog domain signal processing. The correlator include a multiplier which is coupled to an integration capacitance, and an integration reset circuit which is coupled to the integration capacitance. The correlator is designed to receive a first input signal and a second input signal. The multiplier multiplies the first input signal and the second input signal to produce a multiplier output current. The multiplier output current is then integrated by the integration capacitance which produces a correlator output voltage. The integration reset circuit then reset the integration capacitance to a reset voltage.

Interference Cancellation

View page
US Patent:
20160134315, May 12, 2016
Filed:
Nov 10, 2015
Appl. No.:
14/937821
Inventors:
- St. Michael, BB
Gregory T. UEHARA - Kailua HI, US
Marc LEROUX - Austin TX, US
Zhiguo WANG - Austin TX, US
Jari Juhani VAHE - Austin TX, US
Rohit MAINKAR - Austin TX, US
International Classification:
H04B 1/10
H04B 1/12
Abstract:
A circuit comprises a vector separator circuit to generate a first extracted signal according to (i) a first correlation signal, (ii) a second correlation signal, and (iii) a relative response signal. The first correlation signal corresponds to a first correlation between an input signal and a first test signal. The first test signal has a first frequency, and the input signal includes a first spur having the first frequency. The second correlation signal corresponds to a second correlation between the input signal and a second test signal. The second test signal has a second frequency. The relative response signal corresponds to a relative response of the second frequency in the first correlation signal.
Gregory G Uehara from Honolulu, HI, age ~39 Get Report