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Gregg H Jessen

from Amherst, NH
Age ~49
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Also known as:
Gregg H Essen
Related to:
Elliott A Zamott, 48Hazell Sikorski, 52Ingrid A Caine, 75Philip M Jessen, 45Diane J Capparelli, 81Paul E Jessen, 46Angela Marie AnderssonAngela M Capparelli, 49Jack P Capparelli, 81Janice E Jessen, 79Charity L Jessen, 49Gina M Capparelli, 52Lisette M Calvillo, 50Huascar G Jessen, 55Patrik K Andersson, 41
Connected to:
Alexander R Jessen, 31Arne Jessen, 81Arnold G Jessen, 71Brenda J Jessen, 72Chloe Jessen, 63Doreen D Jessen, 71Eleanor G Jessen, 73Elizabeth C Jessen, 70Grace D Jessen, 85Harold W Jessen, 94

Gregg Jessen Phones & Addresses

  • Amherst, NH
  • Beavercreek, OH
  • 1707 Swindon Ct, Fairborn, OH 45324
  • Hilliard, OH
  • Dublin, OH
  • Columbus, OH

Work

Company: Bae systems Jul 2019 Position: Chief scientist at bae systems

Education

Degree: Doctorates, Doctor of Philosophy School / High School: The Ohio State University 1997 to 2002

Skills

Microelectronics • Transistors • Rf Devices • Characterization • Physics • Spectroscopy • Semiconductors • Electronics • Nanotechnology • Materials Science • R&D • Thin Films • Rf • Engineering Management • Electrical Engineering • Design of Experiments • Nanomaterials • Optics • Sensors

Industries

Defense & Space

Resumes

Resumes

Gregg Jessen Photo 1

Chief Scientist At Bae Systems

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Location:
2 Tranquility Ln, Amherst, NH 03031
Industry:
Defense & Space
Work:
Bae Systems
Chief Scientist at Bae Systems
Air Force Research Laboratory
Principal Electronics Engineer
Air Force Research Laboratory Oct 2011 - Jan 2016
Senior Electronics Engineer
Air Force Office of Scientific Research (Afosr) Jun 2008 - Oct 2011
Program Manager
Education:
The Ohio State University 1997 - 2002
Doctorates, Doctor of Philosophy Wright State University 1993 - 1997
Bachelors, Bachelor of Science
Skills:
Microelectronics
Transistors
Rf Devices
Characterization
Physics
Spectroscopy
Semiconductors
Electronics
Nanotechnology
Materials Science
R&D
Thin Films
Rf
Engineering Management
Electrical Engineering
Design of Experiments
Nanomaterials
Optics
Sensors

Publications

Us Patents

Self-Aligned Gate And Drift Design For High-Critical Field Strength Semiconductor Power Transistors With Ion Implantation

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US Patent:
20200357887, Nov 12, 2020
Filed:
May 7, 2020
Appl. No.:
16/869042
Inventors:
- Wright-Patterson AFB OH, US
Andrew J Green - Beavercreek OH, US
Gregg H Jessen - Beavercreek OH, US
International Classification:
H01L 29/08
H01L 29/417
Abstract:
Methods of forming a self-aligned gate (SAG) and self-aligned source (SAD) device for high Esemiconductors are presented. A dielectric layer is deposited on a high Esubstrate. The dielectric layer is etched to form a drift region. A refractory material is deposited on the substrate and dielectric layer. The refractory material is etched to form a gate length. Implant ionization is applied to form high-conductivity and high-critical field strength source with SAG and SAD features. The device is annealed to activate the contact regions. Alternately, a refractory material may be deposited on a high Esubstrate. The refractory material is etched to form a channel region. Implant ionization is applied to form high-conductivity and high Esource and drain contact regions with SAG and SAD features. The refractory material is selectively removed to form the gate length and drift regions. The device is annealed to activate the contact regions.

Highly Integrated Rf Power And Power Conversion Based On Ga2O3 Technology

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US Patent:
20190296000, Sep 26, 2019
Filed:
Jun 10, 2019
Appl. No.:
16/435666
Inventors:
- Wright-Patterson AFB OH, US
Gregg H Jessen - Beavercreek OH, US
International Classification:
H01L 25/18
H01L 23/00
H01L 23/373
H01L 23/14
Abstract:
An integrated circuit is provided including a first substrate with a first thermal conductivity. An active layer is deposited on the first substrate. At least one native device is fabricated on the active layer. A window is formed in the active layer, which exposes a portion of the first substrate. A non-native device is fabricated on a second substrate with a second thermal conductivity lower than the first thermal conductivity. The non-native device is flip-chip mounted in the widow on the first substrate and electrically connected to the at least one native device. The non-native device is also thermally connected to the first substrate such that heat generated by the non-native device is removed through the first substrate.

Highly Integrated Rf Power And Power Conversion Based On Ga2O3 Technology

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US Patent:
20180269194, Sep 20, 2018
Filed:
Mar 15, 2018
Appl. No.:
15/922432
Inventors:
- Wright-Patterson AFB OH, US
Gregg H. Jessen - Beavercreek OH, US
International Classification:
H01L 25/18
H01L 23/00
H01L 23/14
Abstract:
An integrated circuit is provided including a first substrate with a first thermal conductivity. An active layer is deposited on the first substrate. At least one native device is fabricated on the active layer. A window is formed in the active layer, which exposes a portion of the first substrate. A non-native device is fabricated on a second substrate with a second thermal conductivity lower than the first thermal conductivity. The non-native device is flip-chip mounted in the widow on the first substrate and electrically connected to the at least one native device. The non-native device is also thermally connected to the first substrate such that heat generated by the non-native device is removed through the first substrate.

Metal Oxide Thin Film Semiconductor Device Monolithically Integrated With Dissimilar Device On The Same Wafer

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US Patent:
20180254290, Sep 6, 2018
Filed:
Feb 27, 2018
Appl. No.:
15/906322
Inventors:
- Wright-Patterson AFB OH, US
Gregg H. Jessen - Beavercreek OH, US
Kevin D. Leedy - Dayton OH, US
Robert C. Fitch - Xenia OH, US
Andrew J. Green - Beavercreek OH, US
International Classification:
H01L 27/12
H01L 29/786
H01L 23/528
H01L 29/06
H01L 29/20
H01L 29/66
H01L 29/778
H01L 29/205
H01L 29/24
H01L 21/8252
H01L 27/06
Abstract:
A monolithically integrated circuit comprising a semiconducting wafer, a metal oxide thin film semiconductor device disposed adjacent a first region of the semiconducting wafer, and a dissimilar semiconductor device disposed adjacent a second region of the semiconducting wafer and fabrication methods thereof.
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Gregg H Jessen from Amherst, NH, age ~49 Get Report