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Gregg J Armezzani

from Endicott, NY
Age ~68
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Also known as:
Gregg K Armezzani, Greg Armezzani, Gregg I
Phone and address:
1108 Michael Dr, Endicott, NY 13760
(607) 754-0282
Related to:
Becky A Sennett, 62Russell P Esken, 43Francis Armezzani, 94Christopher Sennett, 34Frances Armezzani
Connected to:
Louis T Armezzani, 108Jamie A Armfelt, 70Claude Armfield, 79Nicole J Armfield, 42Dave M Armga, 56James K Armhold, 61Clement E Armi, 79Saleh Armian, 59Travis Armideo, 37Eugen D Armie, 55

Gregg Armezzani Phones & Addresses

  • 1108 Michael Dr, Endicott, NY 13760 (607) 754-0282 (607) 754-4375
  • Endwell, NY
  • Vestal, NY
  • 1108 Michael Dr, Endwell, NY 13760 (607) 434-9438

Work

Company: Bae systems Jan 1, 2006 Position: Program engineering manager ii

Education

Degree: Master of Science, Masters School / High School: Rensselaer Polytechnic Institute 1988 to 1991 Specialities: Engineering

Emails

c***[email protected]

Industries

Electrical/Electronic Manufacturing

Resumes

Resumes

Gregg Armezzani Photo 1

Program Engineering Manager Ii

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Location:
230 Margie Dr, Warner Robins, GA 31088
Industry:
Electrical/Electronic Manufacturing
Work:
Bae Systems
Program Engineering Manager Ii
Endicott Interconnect Technologies, Inc. Nov 2002 - Dec 2005
Engineering Project Manager
Ibm Jun 1979 - Oct 2002
Engineering Project Manager
Education:
Rensselaer Polytechnic Institute 1988 - 1991
Master of Science, Masters, Engineering University of Scranton 1976 - 1979
Bachelors, Bachelor of Science, Electronics Engineering

Publications

Us Patents

Use Of Blind Vias For Soldered Interconnections Between Substrates And Printed Wiring Boards

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US Patent:
6452116, Sep 17, 2002
Filed:
Feb 28, 2001
Appl. No.:
09/796389
Inventors:
Gregg J. Armezzani - Endwell NY
Kishor V. Desai - Fremont CA
Jeffrey S. Perkins - Hauppauge NY
John J. Pessarchick - Binghamton NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01R 909
US Classification:
174262, 174255, 361767
Abstract:
A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of placing one or more blind vias in a first substrate positioned on top of a first conductor; placing one or more blind vias in a second substrate positioned under a second conductor; attaching one or more signal lines to one or more of the one or more blind vias; and assembling ball grid array components such that the first conductor is electrically connected to the second conductor. Also claimed is an electronic circuit package incorporating the blind vias for electrical connection between layers in accordance with the present invention.

Electronic Package With Stacked Connections And Method For Making Same

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US Patent:
6574113, Jun 3, 2003
Filed:
Jan 17, 2001
Appl. No.:
09/764465
Inventors:
Gregg J. Armezzani - Endwell NY
Matthew A. Heller - Raleigh NC
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H05K 710
US Classification:
361767, 361760761-, 361743, 361735, 361790, 361784785-, 361803, 361779, 174260, 174261
Abstract:
An electronic package which includes first and second circuitized substrates secured together by a solder member which includes a first contact portion for attachment to a printed circuit board and a second contact portion used to bond the two substrates together (e. g. , to form a multi-chip module). Semiconductor chips can be positioned on and electrically coupled to the formed solder members.

Electronic Package With Stacked Connections And Method For Making Same

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US Patent:
6617528, Sep 9, 2003
Filed:
Jan 17, 2001
Appl. No.:
09/764476
Inventors:
Gregg J. Armezzani - Endwell NY
Matthew A. Heller - Raleigh NC
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H05K 111
US Classification:
174263, 174257, 174258, 174262, 361767, 361771, 361803
Abstract:
An electronic package which includes first and second circuitized substrates secured together by a solder member which includes a first contact portion for attachment to a printed circuit board and a second contact portion used to bond the two substrates together (e. g. , to form a multi-chip module). Semiconductor chips can be positioned on and electrically coupled to the formed solder members.

Electronic Package With Stacked Connections And Method For Making Same

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US Patent:
6653575, Nov 25, 2003
Filed:
Jan 17, 2001
Appl. No.:
09/764467
Inventors:
Gregg J. Armezzani - Endwell NY
Matthew A. Heller - Raleigh NC
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H05K 114
US Classification:
174262, 174263, 361767, 361768, 361784, 361795, 361803
Abstract:
An electronic package which includes first and second circuitized substrates secured together by a solder member which includes a first contact portion for attachment to a printed circuit board and a second contact portion used to bond the two substrates together (e. g. , to form a multi-chip module). Semiconductor chips can be positioned on and electrically coupled to the formed solder members.

Electronic Package With Stacked Connections

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US Patent:
61986348, Mar 6, 2001
Filed:
Mar 31, 1999
Appl. No.:
9/282842
Inventors:
Gregg J. Armezzani - Endwell NY
Matthew A. Heller - Raleigh NC
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H05K 114
US Classification:
361760
Abstract:
An electronic package which includes first and second circuitized substrates secured together by a solder member which includes a first contact portion for attachment to a printed circuit board and a second contact portion used to bond the two substrates together (e. g. , to form a multi-chip module). Semiconductor chips can be positioned on and electrically coupled to the formed solder members.

Method For Fabricating Chip Carriers And Printed Circuit Boards

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US Patent:
58843973, Mar 23, 1999
Filed:
Aug 6, 1996
Appl. No.:
8/692734
Inventors:
Gregg Joseph Armezzani - Endwell NY
Kishor Vithaldas Desai - Vestal NY
Jeffrey Scott Perkins - Endwell NY
John James Pessarchick - Binghampton NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H05K 334
US Classification:
29840
Abstract:
A method for fabricating a chip carrier and attaching the chip carrier to a printed circuit board is disclosed. A plated through hole (PTH) is formed through a chip carrier substrate. The PTH has surface lands on opposite surfaces of the substrate. Next, at least one of the surfaces of the substrate is covered with a dielectric material. The dielectric material at least partially fills the PTH. A solder ball is attached to the surface land on the opposite side as the dielectric material. Then, a printed circuit board is positioned relative to the chip carrier such that the solder ball contacts a surface land of the printed circuit board. Then, the solder is reflowed. Because the solder is reflowed while the dielectric material at least partially fills the PTH, the dielectric material within the PTH prevents the solder from flowing entirely through the PTH. This prevents contamination of the opposite surface of the chip carrier.

Use Of Blind Vias For Soldered Interconnections Between Substrates And Printed Wiring Boards

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US Patent:
60230290, Feb 8, 2000
Filed:
Mar 19, 1998
Appl. No.:
9/044966
Inventors:
Gregg J. Armezzani - Endwell NY
Kishor V. Desai - Fremont CA
Jeffery S. Perkins - Hauppauge NY
John J. Pessarchick - Binghamton NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H05K 116
US Classification:
174260
Abstract:
A method is provided for connecting two conductive layers in an electronic circuit package including the steps of placing one or more blind vias in a first substrate positioned on top of a first conductor; placing one or more blind vias in a second substrate positioned under a second conductor; attaching one or more signal lines to one or more of the one or more blind vias; and assembling ball grid array components such that the first conductor is electrically connected to the second conductor. Also claimed is an electronic circuit package incorporating the blind vias for electrical connection between layers in accordance with the present invention.

Flexible Thin Film Ball Grid Array Containing Solder Mask

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US Patent:
61876100, Feb 13, 2001
Filed:
Jul 10, 1998
Appl. No.:
9/113573
Inventors:
Gregg Joseph Armezzani - Endwell NY
Robert Nicholas Ives - Guilford NY
Mark Vincent Pierson - Binghamton NY
Terry Alan Tull - Whitney Point NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2144
US Classification:
438106
Abstract:
An electronic package is provided that includes a flexible polyimide film carrier having electronic circuitry on both of its major surfaces and a plurality of solder interconnection pads on a first major surface; solder mask layers located on both major surfaces, provided that areas between subsequently to be applied individual circuit chips on the first major surface exist that are free from the solder mask; and a plurality of modules attached to the film carrier by the solder balls or bumps. Also provided is a method for fabricating the electronic package that includes reflow of the solder balls or bumps to achieve attachment of the modules.
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Gregg J Armezzani from Endicott, NY, age ~68 Get Report