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Glenn G Daves

from Bee Cave, TX
Age ~57

Glenn Daves Phones & Addresses

  • 4532 Mont Blanc Dr, Bee Cave, TX 78738 (512) 712-4203 (845) 838-1540
  • Austin, TX
  • 55 Highland Ct, Fishkill, NY 12524 (845) 838-1540
  • Cold Spring, NY
  • 2 Rockwell Pl, Beacon, NY 12508 (845) 838-1540 (845) 838-2156
  • Champaign, IL
  • New Hamburg, NY
  • Urbana, IL

Public records

Vehicle Records

Glenn Daves

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Address:
4532 Mont Blanc Dr, Bee Cave, TX 78738
Phone:
(512) 712-4203
VIN:
5TDZK23C97S011394
Make:
TOYOTA
Model:
SIENNA
Year:
2007

Resumes

Resumes

Glenn Daves Photo 1

Vice President, Package Innovation

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Location:
Austin, TX
Industry:
Semiconductors
Work:
Freescale Semiconductor since Jul 2008
Director, Packaging Solutions Development

IBM Jun 2007 - Jun 2008
Mgr, Semiconductor Packaging Development

IBM Nov 2004 - Jun 2007
Mgr, Technology Program Management

IBM Jun 2001 - Nov 2004
Mgr, Worldwide Pkg Product Development
Education:
University of Illinois at Urbana-Champaign 1989 - 1991
Alliance Theological Seminary 1993 - 2002
Brown University 1985 - 1989
Skills:
Product Development
Program Management
Cross Functional Team Leadership
Semiconductors
Mems
Engineering Management
Semiconductor Packaging
Semiconductor Industry
Design of Experiments
Electronics
Process Engineering
Manufacturing
Analog
Sensors
Ic
Failure Analysis
Product Management
Leadership
Spc
International Operations
Six Sigma
R&D
Engineering
Product Marketing
Product Engineering
Lean Manufacturing
Glenn Daves Photo 2

Glenn Daves

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Publications

Us Patents

Insulating Interposer Between Two Electronic Components And Process Thereof

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US Patent:
6365977, Apr 2, 2002
Filed:
Aug 31, 1999
Appl. No.:
09/387061
Inventors:
David L. Edwards - Poughkeepsie NY
Norman J. Dauerer - Hopewell Junction NY
Glenn G. Daves - Beacon NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2348
US Classification:
257780, 757781, 757728
Abstract:
The present invention relates generally to a new structure and a method for reducing the cost of producing known good die (KGD). More particularly, the invention encompasses a structure and a method that uses a substrate having solder wettable pads, a chip with attached solder balls, and a thin non-conductive interposer that is assembled between the chip and the substrate. The interposer reduces the cross section of the solder connections from the chip to the substrate where the solder passes through (the holes in) the interposer. This reduced cross-sectional area of the solder connection creates a weak point which allows the chip to be easily sheared off of the substrate after a burn-in and test process. The preferred chips for this invention are flip chips.

Thermal Paste Preforms As A Heat Transfer Media Between A Chip And A Heat Sink And Method Thereof

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US Patent:
6444496, Sep 3, 2002
Filed:
Jul 20, 2000
Appl. No.:
09/619886
Inventors:
David L. Edwards - Poughkeepsie NY
Glenn G. Daves - Beacon NY
Shaji Farooq - Hopewell Junction NY
Sushumna Iruvanti - Wappingers Falls NY
Frank L. Pompeo - Montgomery NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2144
US Classification:
438122, 438584, 257712, 257720, 257746
Abstract:
The present invention relates generally to a new apparatus and method for introducing thermal paste into semiconductor packages. More particularly, the invention encompasses an apparatus and a method that uses at least one preform of thermal paste for the cooling of at least one chip in a sealed semiconductor package. The thermal paste preform is subcooled, and is transferred onto a module component from a separable transfer sheet, or is placed onto the module component using an attached and/or imbedded mesh. The preform of thermal paste may be of simple or complex shape, and enables cooling of one or more chips in a module.

Insulating Interposer Between Two Electronic Components And Process Thereof

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US Patent:
6541365, Apr 1, 2003
Filed:
Nov 14, 2001
Appl. No.:
09/992360
Inventors:
David L. Edwards - Poughkeepsie NY, 12601
Norman J. Dauerer - Hopewell Junction NY, 12533
Glenn G. Daves - Beacon NY, 12508
International Classification:
H01L 2144
US Classification:
438612, 438615, 438118
Abstract:
The present invention relates generally to a new structure and a method for reducing the cost of producing known good die (KGD). More particularly, the invention encompasses a structure and a method that uses a substrate having solder wettable pads, a chip with attached solder balls, and a thin non-conductive interposer that is assembled between the chip and the substrate. The interposer reduces the cross section of the solder connections from the chip to the substrate where the solder passes through (the holes in) the interposer. This reduced cross-sectional area of the solder connection creates a weak point which allows the chip to be easily sheared off of the substrate after a burn-in and test process. The preferred chips for this invention are flip chips.

Jogging Structure For Wiring Translation Between Grids With Non-Integral Pitch Ratios In Chip Carrier Modules

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US Patent:
6762489, Jul 13, 2004
Filed:
Nov 20, 2001
Appl. No.:
09/989666
Inventors:
Glenn G. Daves - Beacon NY
Jason Frankel - Beacon NY
William F. Shutler - Wappingers Falls NY
Anthony Wayne Sigler - Pine Plains NY
Herbert I. Stoller - Poughkeepsie NY
John Vetrero - Marlboro NY
Cathy Ann Zadany - Hopewell Junction NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2348
US Classification:
257692, 257207, 257208, 257211, 257691, 257737, 257786
Abstract:
A jogging structure for translating wiring connections from points in a first grid to corresponding points in a second grid in a chip carrier module is disclosed. In an exemplary embodiment, the structure includes a first translation layer, coupled to the first grid, the first translation layer translating the first grid in an x-axis direction. A second translation layer is coupled to the first translation layer, the second translation layer for translating said wiring connections from the first grid in a y-axis direction, the y-axis direction being orthogonal to the x-axis direction. The second translation layer is further coupled to the second grid.

Method Of Manufacture Of Silicon Based Package

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US Patent:
6878608, Apr 12, 2005
Filed:
May 31, 2001
Appl. No.:
09/870531
Inventors:
Peter J. Brofman - Hopewell Junction NY, US
Glenn G. Daves - Beacon NY, US
Sudipta K. Ray - Wappingers Falls NY, US
Herbert I. Stoller - Poughkeepsie NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L021/46
H01L021/30
H01L021/4763
H01L021/44
H01L021/302
US Classification:
438459, 438455, 438464, 438458, 438637, 438639, 438672, 438689
Abstract:
A silicon based package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Forming via holes which extend through the UTSW, forming metallization in the via holes which extends through the UTSW, making electrical contact to the interconnection structure on the first surface. Then bond the metallization in the via holes to pads of a carrier.

Jogging Structure For Wiring Translation Between Grids With Non-Integral Pitch Ratios In Chip Carrier Modules

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US Patent:
6974722, Dec 13, 2005
Filed:
Apr 7, 2004
Appl. No.:
10/709012
Inventors:
Glenn G. Daves - Beacon NY, US
Jason Frankel - Beacon NY, US
William F. Shutler - Wappingers Falls NY, US
Anthony Wayne Sigler - Pine Plains NY, US
Herbert I. Stoller - Poughkeepsie NY, US
John Vetrero - Marlboro NY, US
Cathy Ann Zadany - Hopewell Junction NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L021/44
H01L021/48
H01L021/50
US Classification:
438106, 438107, 438108
Abstract:
A jogging structure for translating wiring connections from points in a first grid to corresponding points in a second grid in a chip carrier module is disclosed. In an exemplary embodiment, the structure includes a first translation layer, coupled to the first grid, the first translation layer translating the first grid in an x-axis direction. A second translation layer is coupled to the first translation layer, the second translation layer for translating said wiring connections from the first grid in a y-axis direction, the y-axis direction being orthogonal to the x-axis direction. The second translation layer is further coupled to the second grid.

Flexure Plate For Maintaining Contact Between A Cooling Plate/Heat Sink And A Microchip

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US Patent:
7239516, Jul 3, 2007
Filed:
Sep 10, 2004
Appl. No.:
10/939230
Inventors:
David C. Long - Wappingers Falls NY, US
Glenn G. Daves - Fishkill NY, US
David L. Edwards - Poughkeepsie NY, US
Ronald L. Hering - Pleasant Valley NY, US
Sushumna Iruvanti - Wappingers Falls NY, US
Kenneth C. Marston - Wappingers Falls NY, US
Jason S. Miller - Poughkeepsie NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H05K 7/20
US Classification:
361704, 257719, 361710, 361719
Abstract:
A flexible plate for securing a microchip surface to the surface of a cooling device. The flexible plate allows for z-directional movement between the microchip subassembly having a circuit board and a semiconductor substrate, and the cooling device. The flexible plate is a compact, single piece design that provides constraints in alignment in the x-, y-, and theta-directions, while allowing for z-direction compliance and tilt compliance. The flexible plate has tabs for mounting the microchip subassembly and tabs for mounting the cooling device. The microchip tabs are opposite one another and the cooling device mounting tabs are opposite one another. The flexible plate is a one-piece construction made from sheet metal, plastic, or metal castings. The flexible plate has a band with all the tabs mounted on the inside of the band, or one set of tabs mounted on the outside of the band.

Thermal Interface Adhesive And Rework

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US Patent:
7312261, Dec 25, 2007
Filed:
May 11, 2004
Appl. No.:
10/709518
Inventors:
Krishna G. Sachdev - Hopewell Junction NY, US
Daniel George Berger - New Paltz NY, US
Kelly May Chioujones - San Diego CA, US
Glenn Graham Daves - Fishkill NY, US
Hilton T. Toy - Hopewell Junction NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
C08L 63/00
C08K 3/08
C08K 7/00
B32B 27/38
US Classification:
523457, 523435, 525476, 525529, 428414
Abstract:
A reworkable conductive adhesive composition, and method of making such, comprising an epoxy based conductive adhesive containing conductive metal filler particles dispersed in a solvent-free hybrid epoxy polymer matrix. In an additional embodiment an improved method of removing cured conductive polymer adhesives, disclosed here as thermal interface materials, from electronic components for reclamation or recovery of usable parts of module assemblies, particularly high cost semiconductor devices, heat sinks and other module components.
Glenn G Daves from Bee Cave, TX, age ~57 Get Report