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Glen P Gilfeather

from Great Falls, MT
Age ~74
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Also known as:
Glen Patrick Gilfeather, Glen P Gillfeather, Glen R
Phone and address:
3401 4Th Ave S, Great Falls, MT 59405
Related to:
Patrick GilfeatherPatricia J Gilfeather, 72
Connected to:
Brian M Gilfeather, 67Charna E Gilfeather, 66Carole M Gilfedder, 80Mary M Gilfedder, 77Stephen L Gilfedder, 29Walter L Gilfedder, 65Christine A Gilfert, 53Sushma Gilfert, 78Timron E Gilfert, 51Anna M Gilfillan, 67

Glen Gilfeather Phones & Addresses

  • 3401 4Th Ave S, Great Falls, MT 59405
  • Cedar Crest, NM
  • Monarch, MT
  • 187 Hidden Shores Loop, Smithville, TX 78957
  • 428 Mesa Dr, Del Valle, TX 78617 (512) 247-5730
  • Austin, TX
  • 428 Mesa Dr, Del Valle, TX 78617 (512) 695-2099

Work

Company: Gilly's 3d printing Jan 2017 Position: Owner of 3d printing business

Education

Degree: Bachelors, Bachelor of Science School / High School: Montana State University - Bozeman 1975 to 1979 Specialities: Engineering

Skills

Semiconductors • Failure Analysis • Ic • Product Engineering • Asic • Cmos • Analog • Circuit Design • Mixed Signal • Verilog • Debugging • Soc • Vlsi • Pcb Design • Engineering Management • Reliability • Electronics • Analog Circuit Design • Semiconductor Industry • Silicon • Dft • Characterization • Fpga • Simulations • Yield • Integrated Circuit Design • Microelectronics • Design of Experiments • Digital Signal Processors • Microprocessors • Eda • Embedded Systems • Microcontrollers • Processors • Test Engineering • Low Power Design • Hardware Architecture

Emails

g***[email protected]

Industries

Leisure, Travel, & Tourism

Resumes

Resumes

Glen Gilfeather Photo 1

Owner Of 3D Printing Business

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Location:
Great Falls, MT
Industry:
Leisure, Travel, & Tourism
Work:
Gilly's 3D Printing
Owner of 3D Printing Business
At A New Homestead
Leaf Blower, Lawn Mower, and Snow Shoveler
Analytical Solutions Nov 2009 - Mar 2014
Design Analysis Engineer
Edfas 1998 - Nov 2012
Member
Peace With the World May 2006 - Oct 2009
Retired and Traveling
Education:
Montana State University - Bozeman 1975 - 1979
Bachelors, Bachelor of Science, Engineering Great Falls High School 1965 - 1968
Skills:
Semiconductors
Failure Analysis
Ic
Product Engineering
Asic
Cmos
Analog
Circuit Design
Mixed Signal
Verilog
Debugging
Soc
Vlsi
Pcb Design
Engineering Management
Reliability
Electronics
Analog Circuit Design
Semiconductor Industry
Silicon
Dft
Characterization
Fpga
Simulations
Yield
Integrated Circuit Design
Microelectronics
Design of Experiments
Digital Signal Processors
Microprocessors
Eda
Embedded Systems
Microcontrollers
Processors
Test Engineering
Low Power Design
Hardware Architecture

Publications

Us Patents

Probe Grid For Integrated Circuit Excitation

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US Patent:
6352871, Mar 5, 2002
Filed:
Sep 30, 1999
Appl. No.:
09/409089
Inventors:
Rama R. Goruganthu - Austin TX
Jeffrey D. Birdsley - Austin TX
Michael R. Bruce - Austin TX
Brennan V. Davis - Austin TX
Rosalinda M. Ring - Austin TX
Glen Gilfeather - Del Valle TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 2166
US Classification:
438 18, 324754
Abstract:
The ability to excite virtually any portion of semiconductor device is enhanced via a grid formed for exciting circuitry in the semiconductor device. According to an example embodiment of the present invention, a grid having a plurality of narrow probe points is formed extending over target circuitry in a semiconductor device. The grid is accessed and used for exciting various target circuitry within the device by exciting the part of the grid that corresponds to the portion of the target circuitry to which access is desired.

Method And Arrangement For Characterization Of Focused-Ion-Beam Insulator Deposition

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US Patent:
6372627, Apr 16, 2002
Filed:
Aug 26, 1999
Appl. No.:
09/383790
Inventors:
Rosalinda M. Ring - Austin TX
Susan Li - Fremont CA
Glen Gilfeather - Del Valle TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 217463
US Classification:
438622, 438624, 438 18
Abstract:
According to one aspect of the disclosure and a particular example application directed to a flip-chip packaged die, a method for acquiring a signal from a target node in the circuit side includes removing substrate via the back side of the die to form an access area over the target node. A material is deposited in the access area over the target node in such a way to form simultaneously a conductive core and an immediately adjacent insulator. The conductive core is then used to couple a test signal between the target node and the conductive core. Other aspects of the disclosure include using a focused ion-beam system to provide varying concentrations of Gallium in forming simultaneously the conductive core and the immediately adjacent insulator. These aspects significantly lessen integrated circuit analysis and testing procedures.

Probe Grid For Integrated Circuit Analysis

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US Patent:
6455334, Sep 24, 2002
Filed:
Sep 30, 1999
Appl. No.:
09/409982
Inventors:
Rama R. Goruganthu - Austin TX
Jeffrey D. Birdsley - Austin TX
Michael R. Bruce - Austin TX
Brennan V. Davis - Austin TX
Rosalinda M. Ring - Austin TX
Glen Gilfeather - Del Valle TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 2166
US Classification:
438 14, 438 15, 438 17, 438 18, 438108, 438977, 257 48, 257621
Abstract:
The ability to monitor virtually any portion of semiconductor device is enhanced via a grid formed for analyzing circuitry in the semiconductor device. According to an example embodiment of the present invention, a grid having a plurality of narrow probe points is formed extending over target circuitry in a semiconductor device. The grid is accessed and used for monitoring various target circuitry within the device by accessing the part of the grid that corresponds to the portion of the target circuitry to which access is desired.

Time-Resolved Emission Microscopy System

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US Patent:
6469529, Oct 22, 2002
Filed:
May 30, 2000
Appl. No.:
09/580716
Inventors:
Michael R. Bruce - Austin TX
Rama R. Goruganthu - Austin TX
Glen Gilfeather - Del Valle TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G01R 31302
US Classification:
324752, 324750
Abstract:
Integrated circuit devices are analyzed using an integrated system adapted to obtain time-resolved information from the back side of a silicon based semiconductor chip using hot carrier emissions. According to an example embodiment of the present invention, a system is adapted to analyze a semiconductor device under test (DUT) using a plurality of sensors mounted to a microscope having an objective lens. The plurality of sensors include a global acquisition sensor, a single-point acquisition sensor, and a navigation sensor. The integrated system is adapted to use the plurality of sensors individually and simultaneously. The integrated system improves the analysis of the DUT for reasons including that it makes possible the performance of more than one type of analysis simultaneously using a single test arrangement.

Repair Of Resistive Electrical Connections In An Integrated Circuit

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US Patent:
6566888, May 20, 2003
Filed:
Apr 11, 2001
Appl. No.:
09/833250
Inventors:
Michael R. Bruce - Austin TX
Glen Gilfeather - Del Valle TX
Rama R. Goruganthu - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G01R 3108
US Classification:
324525, 324760, 257773, 438 18
Abstract:
The present invention is directed to the repair of resistive circuitry in an integrated circuit die having a multitude of circuit paths. According to an example embodiment of the present invention, a semiconductor die having a resistive electrical connection is analyzed. The location of a circuit portion in the die having a resistive electrical connection is identified. Using the identified location, the resistive circuit portion is annealed and the resistivity of that circuit portion is reduced. The reduced resistivity improves the ability of the die to operate at high speeds, and makes possible the repair and subsequent use of the die in various applications.

Apparatus For Metal Stack Thermal Management In Semiconductor Devices

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US Patent:
6518661, Feb 11, 2003
Filed:
Apr 5, 2001
Appl. No.:
09/826576
Inventors:
Glen Gilfeather - Del Valle TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 23367
US Classification:
257712, 257758, 257713, 257700, 257706, 257719, 257737, 257759, 257774, 361688, 361695, 361696, 361697, 361701, 361702, 361704, 361712, 361717, 361718, 361719, 361720
Abstract:
A semiconductor apparatus includes a semiconductor body in the form of a silicon substrate havng a plurality of active devices. A metal stack including a plurality of metal layers is operatively associated with the active devices. A plurality of conductive elements are connected to the metal stack and to a substrate in the form of for example a printed circuit board. Vias connect conductive elements with respective portions of at least some of the metal layers, with the conductive elements connected to heat absorbing members within the substrate, which is in turn connected to a heat sink external to the substrate, the vias being spaced at regular intervals so as to promote heat dissipation from the metal stack therethrough to the heat absoring members and the heat sink.

Semiconductor Analysis Arrangement And Method Therefor

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US Patent:
6635839, Oct 21, 2003
Filed:
Apr 19, 2001
Appl. No.:
09/838672
Inventors:
Glen P. Gilfeather - Del Valle TX
Srikar V. Chunduri - Austin TX
Brennan V. Davis - Austin TX
David H. Eppes - Austin TX
Victoria Bruce - Austin TX
Michael Bruce - Austin TX
Rosalinda M. Ring - Austin TX
Daniel Stone - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
B07C 500
US Classification:
209576
Abstract:
Semiconductor die analysis is enhanced using a system that is adapted to perturb a die in a test chamber and to detect a response from the die to the perturbation. According to an example embodiment of the present invention, a semiconductor die analysis system includes a test chamber and a docking arrangement adapted to dock with the test chamber. A die is held in the docking arrangement and is presented inside of the test chamber when the docking arrangement is docked with the chamber. Two or more perturbation devices are used to perturb the die, and controller is adapted to control the perturbation. A data acquisition arrangement receives data from the die in response to the perturbation, and the data is used for analyzing the die.

Constant-Current Vddq Testing Of Integrated Circuits

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US Patent:
6661246, Dec 9, 2003
Filed:
Oct 23, 2000
Appl. No.:
09/694523
Inventors:
Glen Patrick Gilfeather - Del Valle TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G01R 3126
US Classification:
324763, 324765, 3241581
Abstract:
Integrated circuit analysis is enhanced via a method and system for detecting defects associated with particular logic states of an integrated circuit. According to an example embodiment of the present invention, a constant current supply is applied to an integrated circuit. The voltage across the constant current supply is detected for each of a plurality of clock cycles of the integrated circuit, each clock cycle being representative of a logic state of the integrated circuit. The voltage detected at each clock cycle is compared, and the comparison is used to analyze the integrated circuit for a defect.
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Glen P Gilfeather from Great Falls, MT, age ~74 Get Report