Gerald G Pechanek

6338129, Jan 8, 2002

Jun 1, 1999

09/323609

Gerald G. Pechanek - Cary NC

BOPS, Inc. - Chapel Hill NC

G06F 1516

712 11

An array processor includes processing elements arranged in clusters which are, in turn, combined in a rectangular array. Each cluster is formed of processing elements which preferably communicate with the processing elements of at least two other clusters. Additionally each inter-cluster communication path is mutually exclusive, that is, each path carries either north and west, south and east, north and east, or south and west communications. Due to the mutual exclusivity of the data paths, communications between the processing elements of each cluster may be combined in a single inter-cluster path. That is, communications from a cluster which communicates to the north and east with another cluster may be combined in one path, thus eliminating half the wiring required for the path. Additionally, the length of the longest communication path is not directly determined by the overall dimension of the array, as it is in conventional torus arrays. Rather, the longest communications path is limited only by the inter-cluster spacing.

6343356, Jan 29, 2002

Oct 9, 1998

09/169255

Gerald G. Pechanek - Cary NC
Edwin F. Barry - Cary NC

BOPS, Inc. - Chapel Hill NC

G06F 930

712210, 712 24, 711173

A reconfigurable register file integrated in an instruction set architecture capable of extended precision operations, and also capable of parallel operation on lower precision data is described. A register file is composed of two separate files with each half containing half as many registers as the original. The halves are designated even or odd by virtue of the register addresses which they contain. Single width and double width operands are optimally supported without increasing the register file size and without increasing the number of register file ports. Separate extended registers are also employed to provide extended precision for operations such as multiply-accumulate operations.

6356994, Mar 12, 2002

Jul 9, 1999

09/350191

Edwin F. Barry - Cary NC
Gerald G. Pechanek - Cary NC

BOPS, Incorporated - Chapel Hill NC

G06F 1500

712 24, 712 11, 712 18, 712 20, 712200, 712210

An indirect VLIW (iVLIW) architecture is described which contains a minimum of two instruction memories. The first instruction memory (SIM) contains short-instruction-words (SIWs) of a fixed length. The second instruction memory (VIM), contains very-long-instruction-words (VLIWs) which allow execution of multiple instructions in parallel. Each SIW may be fetched and executed as an independent instruction by one of the available execution units. A special class of SIW is used to reference the VIM indirectly to either execute or load a specified VLIW instruction (called an âXVâ instruction for âeXecute VLIWâ, or LV for âLoad VLIWâ). In these cases, the SIW instruction specifies how the location of the VLIW is to be accessed. Other aspects of this approach relate to the application of data memory addressing techniques for execution or loading of VLIWs that parallel the addressing modes used for data memory accesses. These addressing techniques provide tremendous flexibility for VLIW instruction execution.

6366997, Apr 2, 2002

Aug 29, 2000

09/649647

Edwin F. Barry - Cary NC
Gerald G. Pechanek - Cary NC
Thomas L. Drabenstott - Chapel Hill NC
Edward A. Wolff - Chapel Hill NC
Nikos P. Pitsianis - Chapel Hill NC
Grayson Morris - Durham NC

BOPS, Inc. - Chapel Hill NC

G06F 1576

712 11, 712 14, 712 16, 712 17, 712 20, 712 21, 712 22, 710131, 710132, 710129

Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used. This control mechanism allows PE register broadcast operations as well as the standard mesh and hypercube communication paths over the same interconnection network. PE to PE communication instructions PEXCHG, SPRECV and SPSEND are also defined and implemented.

6366999, Apr 2, 2002

Jan 28, 1999

09/238446

Thomas L. Drabenstott - Cary NC
Gerald G. Pechanek - Cary NC
Edwin F. Barry - Cary NC

BOPS, Inc. - Chapel Hill NC

G06F 1580

712 24, 712 22, 712 11, 712 14

General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions. Each processor in a multiple processor array may independently have different units conditionally operate based upon their ACFs.

6397324, May 28, 2002

Jun 16, 2000

09/596103

Edwin Frank Barry - Cary NC
Gerald G. Pechanek - Cary NC
Larry D. Larsen - Raleigh NC

BOPS, Inc. - Chapel Hill NC

G06F 9312

712225, 711149, 711220

A very long instruction word (VLIW) processor typically requires a large number of register file ports due to the parallel execution of the sub-instructions comprising the VLIW. By splitting a general purpose register file into separate address and compute register files, the number of compute register file ports is significantly reduced. This reduction is particularly evident when multiple load and store execution units with indexed addressing modes are supported. The implication is that a faster register file and dedicated address registers are achieved in the programming model. The savings comes at the cost of providing support for data movement between the compute register file and the address register file. In addition, address arithmetic, table look-up, and store to table functions are desirable functions that cannot be obviously obtained when the address registers are separated from the compute registers. The present approach provides an efficient mechanism for supporting these functions while maintaining separate compute and address register files.

6405185, Jun 11, 2002

Mar 23, 1995

09/551144

Gerald George Pechanek - Endwell NY
Stamatis Vassiliadis - Vestal NY

International Business Machines Corporation - Armonk NY

G06F 1518

706 41, 706 14, 706 42, 712 19

Image processing for multimedia workstations is a computationally intensive task requiring special purpose hardware to meet the high speed requirements associated with the task. One type of specialized hardware that meets the computation high speed requirements is the mesh connected computer. Such a computer becomes a massively parallel machine when an array of computers interconnected by a network are replicated in a machine. The nearest neighbor mesh computer consists of an NÃN square array of Processor Elements(PEs) where each PE is connected to the North, South, East and West PEs only. The diagonal folded mesh array processor, which is called Oracle, allows the matrix transformation operation to be accomplished in one cycle by simple interchange of the data elements in the dual symmetric processor elements. The use of Oracle for a parallel 2-D convolution mechanish for image processing and multimedia applications and for a finite difference method of solving differential equations is presented, concentrating on the computational aspects of the algorithm.

6408382, Jun 18, 2002

Oct 21, 1999

09/422015

Gerald G. Pechanek - Cary NC
Larry D. Larsen - Raleigh NC

Bops, Inc. - Chapel Hill NC

G06F 945

712227, 341 55, 707 5, 712200

An improved manifold array (ManArray) architecture addresses the problem of configurable application-specific instruction set optimization and instruction memory reduction using an instruction abbreviation process thereby further optimizing the general ManArray architecture for application to high-volume and portable battery-powered type of products. In the ManArray abbreviation process a standard 32-bit ManArray instruction is reduced to a smaller length instruction format, such as 14-bits. An application is first programmed using the full ManArray instruction set using the native 32-bit instructions. After the application program is completed and verified, an instruction-abbreviation tool analyzes the 32-bit application program and generates the abbreviated program using the abbreviated instructions. This instruction abbreviation process allows different program-reduction optimizations tailored for each application program. This process develops an optimized instruction set for the intended application.