Resumes
Resumes
Soc And Ip Verification And Mixed Signal Validation Engineer
View pageLocation:
3032 56Th St, Sacramento, CA 95820
Industry:
Semiconductors
Work:
Intel Corporation
Soc and Ip Verification and Mixed Signal Validation Engineer
Intel Corporation Jun 2010 - Jan 2011
Graduate Technical Intern: Mixed Signal Validation
Texas A&M University Aug 2009 - Jan 2010
Graduate Teaching Assistant
Applied Research Laboratories at the University of Texas Pickle Research Campus Jun 2005 - Aug 2009
Student Technician
Soc and Ip Verification and Mixed Signal Validation Engineer
Intel Corporation Jun 2010 - Jan 2011
Graduate Technical Intern: Mixed Signal Validation
Texas A&M University Aug 2009 - Jan 2010
Graduate Teaching Assistant
Applied Research Laboratories at the University of Texas Pickle Research Campus Jun 2005 - Aug 2009
Student Technician
Education:
Texas A&M University 2009 - 2011
Masters, Electrical Engineering, Engineering, Design The University of Texas at Austin 2005 - 2009
Bachelors, Bachelor of Science, Electrical Engineering Westlake High School 2001 - 2005
Masters, Electrical Engineering, Engineering, Design The University of Texas at Austin 2005 - 2009
Bachelors, Bachelor of Science, Electrical Engineering Westlake High School 2001 - 2005
Skills:
Simulations
Mixed Signal
Systemverilog
Perl
Matlab
C
Verilog
Pcie
Vlsi
Computer Architecture
Cadence Virtuoso
Specman
Debugging
Analog
Cadence
Linux
Intel
Spice
Unix
Functional Verification
Tcl
Programming
Shell Scripting
Rtl Coding
Awk
Sed
Unix Utilities
Circuit Design
Verilog Ams
C++
Bash
Python
Grep
Vim
Regular Expressions
Open Verification Methodology
Object Oriented Languages
Rtl Verification
Test Environment Setup
Vcs
Monte Carlo Simulation
Test Automation
Assertion Based Verification
Test Coverage
Upf
Vcs Nlp
Power Aware Verification
Very Large Scale Integration
Cmos
Mixed Signal
Systemverilog
Perl
Matlab
C
Verilog
Pcie
Vlsi
Computer Architecture
Cadence Virtuoso
Specman
Debugging
Analog
Cadence
Linux
Intel
Spice
Unix
Functional Verification
Tcl
Programming
Shell Scripting
Rtl Coding
Awk
Sed
Unix Utilities
Circuit Design
Verilog Ams
C++
Bash
Python
Grep
Vim
Regular Expressions
Open Verification Methodology
Object Oriented Languages
Rtl Verification
Test Environment Setup
Vcs
Monte Carlo Simulation
Test Automation
Assertion Based Verification
Test Coverage
Upf
Vcs Nlp
Power Aware Verification
Very Large Scale Integration
Cmos
Languages:
English