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George H Robbert

from Fort Collins, CO
Age ~61
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Also known as:
George Harold Robbert, Robert George
Phone and address:
2245 Iroquois Dr, Fort Collins, CO 80525
Related to:
Mary R Ambrosoli, 66Carrie Marie EorgeGeorge Wright, 73Edwin GeorgeLonnie George, 70
Connected to:
Brad G Robbert, 51Bradlee J Robbert, 44James E Robbert, 76Jason L Robberts, 47John P Robbert, 54Julie A Robberts, 61Sandra J Robberts, 76Steven F Robberts, 63Carol L Robbie, 63Don Robbie, 101

George Robbert Phones & Addresses

  • 2245 Iroquois Dr, Fort Collins, CO 80525
  • Saint Louis, MO
  • Ballwin, MO
  • 709 S Skinker Blvd APT 701, Saint Louis, MO 63105

Publications

Us Patents

System And Method For Controlling Activity Of Temporary Files In A Computer System

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US Patent:
6957367, Oct 18, 2005
Filed:
Aug 30, 2002
Appl. No.:
10/231529
Inventors:
S. Brandon Keller - Evans CO, US
Gregory Dennis Rogers - Fort Collins CO, US
George Harold Robbert - Fort Collins CO, US
Assignee:
Hewlett-Packard Development Company L.P. - Houston TX
International Classification:
G06F011/00
US Classification:
714 48, 717124
Abstract:
A method for controlling activity of a temporary file associated with a target file to which data is to be written.

System And Method For Iteratively Traversing A Hierarchical Circuit Design

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US Patent:
7032206, Apr 18, 2006
Filed:
Aug 25, 2003
Appl. No.:
10/647688
Inventors:
S. Brandon Keller - Evans CO, US
Gregory Dennis Rogers - Fort Collins CO, US
George Harold Robbert - Fort Collins CO, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 17/50
US Classification:
716 12
Abstract:
Systems, methods, and software products iteratively traverse a hierarchical circuit design. An initial net and an instance history that uniquely defines the initial net within the design are selected. The initial net and the instance history are appended to a list of nets to be processed. The initial net and the instance history are inserted into a set of visited nets. Each additional net connected to the initial net is visited in response to a first request from a user. The initial net and each additional net are returned in response to a second request from the user.

System And Method For Determining Wire Capacitance For A Vlsi Circuit

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US Patent:
7047507, May 16, 2006
Filed:
Aug 25, 2003
Appl. No.:
10/647597
Inventors:
S. Brandon Keller - Evans CO, US
Gregory Dennis Rogers - Fort Collins CO, US
George Harold Robbert - Fort Collins CO, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 17/50
G06F 9/45
US Classification:
716 5, 716 4, 716 6
Abstract:
A method and system for determining wire capacitance for a VLSI circuit design, comprising determining all hierarchical blocks of a portion of the design; storing, for a plurality of the blocks, indicia of the most accurate one of a plurality of wire capacitance data sources; generating a wire capacitance database with an entry for each net in at least a plurality of the blocks, using information stored in at least one of the wire capacitance data sources; generating a hierarchical connectivity model for the design; and using the hierarchical connectivity model and said wire capacitance database to determine a cumulative wire capacitance value for each HLSN in each of the blocks in a portion of the design to be analyzed.

Systems And Methods Utilizing Fast Analysis Information During Detailed Analysis Of A Circuit Design

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US Patent:
7058908, Jun 6, 2006
Filed:
Aug 25, 2003
Appl. No.:
10/647687
Inventors:
S. Brandon Keller - Evans CO, US
Gregory Dennis Rogers - Fort Collins CO, US
George Harold Robbert - Fort Collins CO, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 9/45
G06F 17/50
US Classification:
716 4, 716 5
Abstract:
Systems, methods, software products utilize fast analysis information during detailed analysis of a circuit design. One or more design blocks of the circuit design are electronically analyzed to determine fast analysis results based upon assumptions of ported signal nets of each one of the design blocks. Next, it is determined whether hierarchical signal net connectivity of block instances of the design blocks and the assumptions match. If the hierarchical signal net connectivity matches the assumptions, the fast analysis results are utilized to generate detailed analysis results. If the hierarchical signal net connectivity does not match the assumptions, the one or more blocks in the hierarchical signal net connection are electronically analyzed to generate detailed analysis results.

Computer Aided Design Systems And Methods With Reduced Memory Utilization

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US Patent:
7062727, Jun 13, 2006
Filed:
Aug 25, 2003
Appl. No.:
10/647598
Inventors:
S. Brandon Keller - Evans CO, US
Gregory Dennis Rogers - Fort Collins CO, US
George Harold Robbert - Fort Collins CO, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 17/50
US Classification:
716 1, 716 2, 711133
Abstract:
Methods, systems, software products analyze a circuit design with reduced memory utilization. Access to at least one block of the circuit design is detected. If the one block is not loaded within a circuit model of computer memory, a determination is made whether loading the one block into the circuit model would exceed a predefined maximum utilization of the computer memory. If loading the one block into the circuit model would exceed the predefined maximum utilization, one or more blocks from the circuit model are unloaded and the one block is loaded into the circuit model. If loading the one block into the circuit model would not exceed the predefined maximum utilization, the one block is loaded into the circuit model.

System And Method For Determining A Highest Level Signal Name In A Hierarchical Vlsi Design

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US Patent:
7073152, Jul 4, 2006
Filed:
Aug 25, 2003
Appl. No.:
10/647768
Inventors:
S. Brandon Keller - Evans CO, US
Gregory Dennis Rogers - Fort Collins CO, US
George Harold Robbert - Fort Collins CO, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 17/50
US Classification:
716 12
Abstract:
Systems, methods, and software products determine a highest level signal name in a hierarchical circuit design. A signal path is traced into a hierarchically lower level of the circuit design from a predetermined net in the circuit design to a predetermined terminal instance, while adding indicia, to an instance history list, of each subsequent instance encountered. A port instance is determined on the terminal instance associated with a selected net for which the highest level signal name is to be determined. The selected net is designated as the current net. For each stored indicia in the instance history list, the net connected to the current net in a hierarchical parent of the instance identified by the indicia is determined, to establish a next current net. If a condition exists wherein there is no connection from the current net to a hierarchically higher level instance, then the current net is established as the highest level signal name for the selected net.

System And Method For Determining Unmatched Design Elements In A Computer-Automated Design

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US Patent:
7076752, Jul 11, 2006
Filed:
Aug 25, 2003
Appl. No.:
10/647608
Inventors:
S. Brandon Keller - Evans CO, US
Gregory Dennis Rogers - Fort Collins CO, US
George Harold Robbert - Fort Collins CO, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 17/50
US Classification:
716 5
Abstract:
A system and method for determining unmatched design elements in a circuit. The system determines instances of a first type and a second type of the design elements that are connected to a specific node in the circuit, and stores the gate signal name for each determined said occurrence of the first type of design element in a first list. The gate signal name for each determined said occurrence of the second type of design element is than stored in a second list. A value of a design element characteristic and indicia thereof for each determined said occurrence of the first and the second types of the design elements is than stored. A set difference operation is preformed on the first list and the second list to determine orphan gate signal names that appear in only one said list; and a cumulative value is determined for each said design element characteristic, by adding the design element characteristic value corresponding to each stored said orphan gate signal name, to produce a total design element characteristic value.

Systems And Methods For Determining Activity Factors Of A Circuit Design

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US Patent:
7086019, Aug 1, 2006
Filed:
Aug 25, 2003
Appl. No.:
10/647594
Inventors:
S. Brandon Keller - Evans CO, US
Gregory Dennis Rogers - Fort Collins CO, US
George Harold Robbert - Fort Collins CO, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 17/50
US Classification:
716 4, 716 5, 716 6
Abstract:
Systems, methods and software products determine activity factors of a circuit design. An activity factor is assigned to one or more node types. One or more signal nets from a netlist of the circuit design are read. The signal nets are processed to associate one of the node types with each of the signal nets. An activity factor is determined for each of the signal nets based upon node type.
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George H Robbert from Fort Collins, CO, age ~61 Get Report