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George D Papasouliotis

from Lake Oswego, OR
Age ~60
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Related to:
Benjamin K Kindzia, 49Josephine A Borczynski, 70
Connected to:
Penelope Papasotiriou, 66Demetra Papastamatatos, 32Christopher K Papathanasiou, 41Dimitra M Papathanasiou, 34Kostas Papathanasiou, 52Quintin Papathakis, 34Athan N Papatheodore, 68Katerina Papatheodorou, 35Sokol Papathimiu, 55Michael F Papatonis, 56

George Papasouliotis Phones & Addresses

  • Lake Oswego, OR
  • 14 Foxglove Dr, Warren, NJ 07059 (908) 647-5237
  • Somerset, NJ
  • 135 Laconia Cir, North Andover, MA 01845 (978) 208-1860
  • Peabody, MA
  • Sunnyvale, CA
  • Cupertino, CA
  • Rochester, NY
  • Fishkill, NY
  • 14 Foxglove Dr, Warren, NJ 07059

Work

Company: Veeco instruments Jul 2011 Position: Senior director of technology

Education

Degree: PhD School / High School: University of Rochester 1989 to 1996 Specialities: Chemical Engineering

Skills

Thin Films • Process Simulation • Plasma Physics • Surface Chemistry • Semiconductors • Atomic Layer Deposition • Silicon • Process Engineering • Materials Science • Materials • Characterization • Metrology • Design of Experiments • Product Marketing • Semiconductor Industry • Cvd • Process Integration • R&D • Electronics • Nanotechnology • Research and Development • Failure Analysis • Chemical Vapor Deposition • Optics • Mems • Ic • Strategic Planning • Strategic Partnerships • Technology Roadmapping • Organizational Development • Organizational Leadership • Organizational Design • Strategic Roadmaps

Languages

English • Greek • German

Industries

Semiconductors

Resumes

Resumes

George Papasouliotis Photo 1

Director

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Location:
16686 Maple Cir, Lake Oswego, OR 97034
Industry:
Semiconductors
Work:
Veeco Instruments since Jul 2011
Senior Director of Technology
Varian Semiconductor Jan 2006 - Jun 2011
Director of Plasma Doping Technology
Novellus Systems May 1996 - Jan 2006
Sr. Process Development Manager
Education:
University of Rochester 1989 - 1996
PhD, Chemical Engineering Aristoteleio University of Thessaloniki 1983 - 1989
Diploma in Chemical Engineering, Chemical Engineering
Skills:
Thin Films
Process Simulation
Plasma Physics
Surface Chemistry
Semiconductors
Atomic Layer Deposition
Silicon
Process Engineering
Materials Science
Materials
Characterization
Metrology
Design of Experiments
Product Marketing
Semiconductor Industry
Cvd
Process Integration
R&D
Electronics
Nanotechnology
Research and Development
Failure Analysis
Chemical Vapor Deposition
Optics
Mems
Ic
Strategic Planning
Strategic Partnerships
Technology Roadmapping
Organizational Development
Organizational Leadership
Organizational Design
Strategic Roadmaps
Languages:
English
Greek
German

Publications

Us Patents

Pulsed Deposition Layer Gap Fill With Expansion Material

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US Patent:
7288463, Oct 30, 2007
Filed:
Apr 28, 2006
Appl. No.:
11/414459
Inventors:
George D. Papasouliotis - Peabody MA, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L 21/762
US Classification:
438431, 438758, 438788, 438432, 257E21631
Abstract:
Conformal dielectric deposition processes supplemented with a deposited expansion material can fill high aspect ratio narrow width gaps with significantly reduced incidence of voids or weak spots. The technique can also be used generally to form composites, such as for the densification of any substrate having open spaces or gaps to be filled without the incidence of voids or seams.

Conformal Nanolaminate Dielectric Deposition And Etch Bag Gap Fill Process

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US Patent:
7482247, Jan 27, 2009
Filed:
Sep 19, 2006
Appl. No.:
11/524502
Inventors:
George D. Papasouliotis - North Andover MA, US
Raihan M. Tarafdar - San Jose CA, US
Dennis M. Hausmann - Lake Oswego OR, US
Jeff Tobin - Mountain View CA, US
Adrianne K. Tipton - Pleasanton CA, US
Bunsen Nie - Fremont CA, US
Brian G. Lu - Fremont CA, US
Timothy M. Archer - Lake Oswego OR, US
Sasson Roger Somekh - Los Altos Hills CA, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L 21/311
US Classification:
438437, 438789, 257E21245, 257E21546
Abstract:
Conformal nanolaminate dielectric deposition and etch back processes that can fill high aspect ratio (typically at least 5:1, for example 6:1), narrow width (typically sub 0. 13 micron, for example 0. 1 micron or less) gaps with significantly reduced incidence of voids or weak spots involve the use of any suitable confirmal dielectric deposition technique and a dry etch back. The etch back part of the process involves a single step or an integrated multi-step (for example, two-step) procedure including an anisotropic dry etch followed by an isotropic dry etch. The all dry deposition and etch back process in a single tool increases throughput and reduces handling of wafers resulting in more efficient and higher quality nanolaminate dielectric gap fill operations.

Closed Loop Control And Process Optimization In Plasma Doping Processes Using A Time Of Flight Ion Detector

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US Patent:
7586100, Sep 8, 2009
Filed:
Feb 12, 2008
Appl. No.:
12/029710
Inventors:
Deven M. Raj - Wenham MA, US
Ludovic Godet - Wakefield MA, US
Bernard Lindsay - Danvers MA, US
Timothy Miller - Ipswich MA, US
George Papasouliotis - North Andover MA, US
Assignee:
Varian Semiconductor Equipment Associates, Inc. - Gloucester MA
International Classification:
H01J 49/40
G01N 27/26
H01L 21/31
H01L 21/469
US Classification:
250423R, 250424, 250425, 250397, 2504923, 31511121, 118620, 438513, 356316
Abstract:
A method of controlling a plasma doping process using a time-of-flight ion detector includes generating a plasma comprising dopant ions in a plasma chamber proximate to a platen supporting a substrate. The platen is biased with a bias voltage waveform having a negative potential that attracts ions in the plasma to the substrate for plasma doping. A spectrum of ions present in the plasma is measured as a function of ion mass with a time-of-flight ion detector. The total number ions impacting the substrate is measured with a Faraday dosimetry system. An implant profile is determined from the measured spectrum of ions. An integrated dose is determined from the measured total number of ions and the calculated implant profile. At least one plasma doping parameter is modified in response to the calculated integrated dose.

Method Of Selective Coverage Of High Aspect Ratio Structures With A Conformal Film

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US Patent:
7625820, Dec 1, 2009
Filed:
Jun 21, 2006
Appl. No.:
11/473372
Inventors:
George D. Papasouliotis - North Andover MA, US
Mihai Buretea - San Francisco CA, US
Collin Mui - Mountain View CA, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L 21/44
US Classification:
438677, 438681, 257E21553
Abstract:
Methods for forming thin dielectric films by selectively depositing a conformal film of dielectric material on a high aspect ratio structure have uses in semiconductor processing and other applications. A method for forming a dielectric film involves providing in a deposition reaction chamber a substrate having a gap on the surface. The gap has a top opening and a surface area comprising a bottom and sidewalls running from the top to the bottom. A conformal silicon oxide-based dielectric film is selectively deposited in the gap by first preferentially applying a film formation catalyst or a catalyst precursor on a portion representing less than all of the gap surface area. The substrate surface is then exposed to a silicon-containing precursor gas such that a silicon oxide-based dielectric film layer is preferentially formed on the portion of the gap surface area. The preferential application of the catalyst or catalyst precursor may occur either at the top of the gap, for example to form a sacrificial mask, or at the bottom of the gap to create a seamless and void-free gap fill.

Profile Adjustment In Plasma Ion Implanter

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US Patent:
7687787, Mar 30, 2010
Filed:
Nov 7, 2008
Appl. No.:
12/267193
Inventors:
Ludovic Godet - North Reading MA, US
George D. Papasouliotis - North Andover MA, US
Ziwei Fang - Beverly MA, US
Richard Appel - Danvers MA, US
Vincent Deno - Gloucester MA, US
Vikram Singh - North Andover MA, US
Harold M. Persing - Rockport MA, US
Assignee:
Varian Semiconductor Equipment Associates, Inc. - Gloucester MA
International Classification:
H01J 37/317
H01L 21/265
H05H 1/24
US Classification:
25049221, 2504922, 250423 R, 250424, 438510, 31511121, 118723 E, 118723 R
Abstract:
A method to provide a dopant profile adjustment solution in plasma doping systems for meeting both concentration and junction depth requirements. Bias ramping and bias ramp rate adjusting may be performed to achieve a desired dopant profile so that surface peak dopant profiles and retrograde dopant profiles are realized. The method may include an amorphization step in one embodiment.

Implantation Of Multiple Species To Address Copper Reliability

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US Patent:
7737013, Jun 15, 2010
Filed:
Oct 21, 2008
Appl. No.:
12/255181
Inventors:
Heyun Yin - Saugus MA, US
George D. Papasouliotis - North Andover MA, US
Vikram Singh - North Andover MA, US
Assignee:
Varian Semiconductor Equipment Associates, Inc. - Gloucester MA
International Classification:
H01L 21/00
US Classification:
438527, 438643, 438687, 257E21584
Abstract:
A first species and a second species are implanted into a conductor of a substrate, which may be copper. The first species and second species may be implanted sequentially or at least partly simultaneously. Diffusion of the first species within the conductor of the substrate is prevented by the presence of the second species. In one particular example, the first species is silicon and the second species is nitrogen, although other combinations are possible.

Sequential Deposition/Anneal Film Densification Method

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US Patent:
7790633, Sep 7, 2010
Filed:
Sep 11, 2006
Appl. No.:
11/519445
Inventors:
Raihan M. Tarafdar - San Jose CA, US
George D. Papasouliotis - North Andover MA, US
Ron Rulkens - Milpitas CA, US
Dennis M. Hausmann - Lake Oswego OR, US
Jeff Tobin - Mountain View CA, US
Adrianne K. Tipton - Pleasanton CA, US
Bunsen Nie - Fremont CA, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L 21/31
H01L 21/469
US Classification:
438788, 438799, 257E21471, 257E21625
Abstract:
A silicon dioxide-based dielectric layer is formed on a substrate surface by a sequential deposition/anneal technique. The deposited layer thickness is insufficient to prevent substantially complete penetration of annealing process agents into the layer and migration of water out of the layer. The dielectric layer is then annealed, ideally at a moderate temperature, to remove water and thereby fully densify the film. The deposition and anneal processes are then repeated until a desired dielectric film thickness is achieved.

Method Of Selective Coverage Of High Aspect Ratio Structures With A Conformal Film

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US Patent:
7863190, Jan 4, 2011
Filed:
Nov 20, 2009
Appl. No.:
12/623333
Inventors:
George D. Papasouliotis - North Andover MA, US
Mihai Buretea - San Francisco CA, US
Collin Mui - Mountain View CA, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L 21/44
US Classification:
438677, 438661, 257E21553
Abstract:
Methods for forming thin dielectric films by selectively depositing a conformal film of dielectric material on a high aspect ratio structure have uses in semiconductor processing and other applications. A method for forming a dielectric film involves providing in a deposition reaction chamber a substrate having a gap on the surface. The gap has a top opening and a surface area comprising a bottom and sidewalls running from the top to the bottom. A conformal silicon oxide-based dielectric film is selectively deposited in the gap by first preferentially applying a film formation catalyst or a catalyst precursor on a portion representing less than all of the gap surface area. The substrate surface is then exposed to a silicon-containing precursor gas such that a silicon oxide-based dielectric film layer is preferentially formed on the portion of the gap surface area. The preferential application of the catalyst or catalyst precursor may occur either at the top of the gap, for example to form a sacrificial mask, or at the bottom of the gap to create a seamless and void-free gap fill.
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George D Papasouliotis from Lake Oswego, OR, age ~60 Get Report