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George A Lerom

from Austin, TX
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Also known as:
George E Lerom, G Lerom
Phone and address:
11212 Taterwood Dr, Austin, TX 78750
(512) 258-0485
Connected to:
Ryan Lerone, 48Darren C Lerose, 50Gregory R Lerouge, 79Adam D Leroux, 42Aimee J Leroux, 42Aletta H Leroux, 55Andreia F Leroux, 36Anthony M Leroux, 39Blesson H Leroux, 58Bobby C Leroux, 52

George Lerom Phones & Addresses

  • 11212 Taterwood Dr, Austin, TX 78750 (512) 258-0485
    • s
  • 1515 Verano Dr, Dallas, TX 75218
  • 27038 Highway 145, Dolores, CO 81323 (970) 562-3844
  • Houston, TX
  • 1818A Woodsman Dr, College Station, TX 77840
  • 11212 Taterwood Dr, Austin, TX 78750

Work

Company: Ibm Position: Retired

Skills

Information Technology

Industries

Information Technology And Services

Resumes

Resumes

George Lerom Photo 1

George Lerom

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Location:
Dallas, TX
Industry:
Information Technology And Services
Work:
Ibm
Retired
Skills:
Information Technology

Publications

Us Patents

I/O Cache Controller Containing A Buffer Memory Partitioned Into Lines Accessible By Corresponding I/O Devices And A Directory To Track The Lines

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US Patent:
54189276, May 23, 1995
Filed:
Dec 23, 1992
Appl. No.:
7/996501
Inventors:
Albert Chang - Austin TX
George A. Lerom - Austin TX
James O. Nicholson - Austin TX
John C. O'Quin - Austin TX
John T. O'Quin - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1214
G06F 1300
US Classification:
345425
Abstract:
A cache for use with input/output devices attached to an input/output bus. Requests for access to system memory by an input/output device pass through the cache. Access authority is checked to determine whether an input/output device is authorized to access that particular page. If it is not, access is denied. Each input/output device has access to a portion of the cache, so that activity by one device will not interfere with activity by another.

Data Processor Having Multiple-Buffer Adapter Between A System Channel And An Input/Output Bus

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US Patent:
45716714, Feb 18, 1986
Filed:
May 13, 1983
Appl. No.:
6/494250
Inventors:
Charles S. Burns - Mazeppa MN
Michael R. Crabtree - Rochester MN
Dwight A. Gourneau - Rochester MN
Scott W. Hinkel - Rochester MN
George A. Lerom - Austin TX
Michael J. Mayfield - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 300
US Classification:
364200
Abstract:
A data processor has a block-multiplexed system channel coupled to a processing engine and a byte-multiplexed bus coupled to multiple I/O devices. A multi-buffer adapter transfers data by cycle-steal (direct memory access) operations between the channel and the bus. The adapter has multiple buffers switchable to the channel in a burst mode by a channel interface and to the bus in a byte mode by a device-level interface.

High Speed Data Transfer System Which Adjusts Data Transfer Speed In Response To Indicated Transfer Speed Capability Of Connected Device

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US Patent:
52376761, Aug 17, 1993
Filed:
Jan 13, 1989
Appl. No.:
7/297773
Inventors:
Ravi K. Arimilli - Round Rock TX
Sudhir Dhawan - Austin TX
George A. Lerom - Austin TX
James O. Nicholson - Austin TX
David W. Siegel - Austin TX
Assignee:
International Business Machines Corp. - Armonk NY
International Classification:
G06F 1314
US Classification:
395550
Abstract:
A computer system bus includes signal lines for controlling a high speed block data transfer mode between a bus master and a bus slave. When both devices support such a transfer, a high speed bus clock separate from the normal bus clock is used to transfer data. Devices not involved in the high speed block transfer see only an extended normal data transfer. The master and slave use bus control signals to determine the speed and data width of the high speed transfer. If the slave is unable to transfer the complete block of data at the high speed clock rate, it can signal the master to repeat the transfer of individual data items as necessary.
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George A Lerom from Austin, TX Get Report