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George A Drapac

from Cleveland, TN
Age ~75
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Also known as:
George R Drapac
Related to:
Teri L Sims, 53Justin E Noles, 33Judy L Drapac, 66Andrew DrapachSophie DrapachSophie DrapachJudy L Drapac, 70Therese M Drapach, 70
Connected to:
Joseph P Drapac, 46Mark A Drapak, 63Dawn M Drapala, 43Michael A Drapala, 38Beverly B Drapalik, 66Michael Drapalla, 63Sigla Drapanauskaite, 31John J Drapaniotis, 40Vlada Drapatsky, 54Geoffrey A Drapcak, 48

George Drapac Phones & Addresses

  • Cleveland, TN
  • North Lauderdale, FL
  • Tamarac, FL
  • Pensacola, FL
  • 6230 Amberwoods Dr, Boca Raton, FL 33433 (561) 393-6614
  • 204 Alecia Ln SE, Cleveland, TN 37323 (561) 644-2400

Work

Position: Food Preparation and Serving Related Occupations

Education

Degree: Associate degree or higher

Resumes

Resumes

George Drapac Photo 1

Memeber Of The Technical Staff

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Location:
Cleveland, TN
Work:

Memeber of the Technical Staff
George Drapac Photo 2

George Drapac

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Publications

Us Patents

Backup Battery System For A Portable Electronic Device

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US Patent:
53999568, Mar 21, 1995
Filed:
Feb 3, 1992
Appl. No.:
7/829833
Inventors:
Michael J. DeLuca - Boca Raton FL
Mark L. Oliboni - Boynton Beach FL
George A. Drapac - Boca Raton FL
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G05F 146
US Classification:
323222
Abstract:
In a device having a primary battery 10, a first voltage multiplier 20 is used to power digital electrical circuits 40 from the primary battery, and a second voltage multiplier 100-136 is used to recharge a backup battery 50 from the primary battery. The backup battery is charged to a voltage greater than the voltage generated by the first voltage multiplier. Methods of controlling the second voltage multiplier reduce its interference in measurement of device parameters, and reduce the power consumed from the primary battery.

Driver Circuit Providing Controllable Battery Overload Protection

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US Patent:
57449848, Apr 28, 1998
Filed:
Nov 13, 1996
Appl. No.:
8/748641
Inventors:
George A. Drapac - Boca Raton FL
Keith E. Jackoski - Wellington FL
Paul J. Godfrey - Melbourne FL
Gary L. Pace - Boca Raton FL
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H03K 5153
US Classification:
327 89
Abstract:
A driver circuit (100) is utilized to drive a high current load (116) in an electronic device powered by a battery (118) having a terminal voltage which varies in relation to a level of energy being consumed. The driver circuit (100) includes a differential amplifier (110) which is responsive to a predetermined reference voltage and to the terminal voltage for generating a drive control signal which proportionally reduces a current supplied to the high current load (114) when the terminal voltage is substantially equal to and lower than the predetermined reference voltage. A slope control element (112) is coupled to the differential amplifier (110) to control a rate at which the drive control signal reduces proportionally the current supplied to the high current load (116). A load control element (114), coupled to the differential amplifier (100), provides the supply of current to the high current load (116).

Radio Signal Receiving Apparatus With A Security Circuitry

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US Patent:
43785514, Mar 29, 1983
Filed:
Dec 5, 1980
Appl. No.:
6/213523
Inventors:
George Drapac - Tamarac FL
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H04Q 130
G08B 522
US Classification:
3403111
Abstract:
A radio signal receiving apparatus such as a pager with a security circuitry includes operator-controlled switches for providing a plurality of different command signals which are used to actuate the receiving apparatus in a different mode of operation, an interface circuitry with an optional feature circuitry coupled to the receiving circuitry of the apparatus for providing various optional functions such as automatic reset, single/dual function or battery saving functions to the receiving apparatus, and a security circuitry for preventing the receiving apparatus from receiving the incoming signal once tampering of the optional feature security is detected.

Programmable Multi-Address Pager Receiver And Method Of Characterizing Same

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US Patent:
49756931, Dec 4, 1990
Filed:
Jan 30, 1989
Appl. No.:
7/303889
Inventors:
Walter L. Davis - Coral Springs FL
George Drapac - Boca Raton FL
Stephen H. Woltz - Boca Raton FL
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G08B 522
H04Q 302
US Classification:
34082544
Abstract:
The pager receiver including a conventional address decoder, an alert envelope waveform generator, and an alert function mapper is disclosed. The pager is individually and uniquely characterized by programming the alert function mapper to govern the generation of assigned alert annunciation patterns by the waveform generator in response to selected decoded pager addresses and associated functions thereof, and to inhibit alert generation by the waveform generator in response to non-selected decoded pager addresses and associated functions thereof. In one embodiment, the alert signal waveform generator is enabled to respond to the alert function mapper only when the pager address is decoded by the decoder.

Battery Saving Apparatus And Method Providing Optimum Synchronization Codeword Detection

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US Patent:
49610732, Oct 2, 1990
Filed:
Feb 27, 1989
Appl. No.:
7/315957
Inventors:
George Drapac - Boca Raton FL
Stephen H. Woltz - Boca Raton FL
Mark L. Oliboni - Boynton Beach FL
Assignee:
Motorola, Inc. - Schaumburg DE
International Classification:
H04B 700
US Classification:
34082544
Abstract:
A battery saving apparatus for supplying power to a selective call communication receiver for enabling the detection of a synchronization codeword in data received in a predetermined signaling format comprises circuits for supplying power to the receiver, and for detecting valid data received during a first portion of the first predetermined time interval. Power is maintained to the receiver for the remainder of the first predetermined time interval when valid data is detected in the first portion. A synchronization codeword detector is included for detecting a synchronization codeword. When valid data is subsequently detected following a second portion of the first predetermined time interval and the synchronization codeword is not detected in the first predetermined time interval, power is maintained to the receiver for a second predetermined time interval to further enable detection of the synchronization codeword.

Paging Device With Alternating Alert Outputs

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US Patent:
H11738, Apr 6, 1993
Filed:
Oct 8, 1991
Appl. No.:
7/772640
Inventors:
Walter L. Davis - Coral Springs FL
George Drapac - Boca Raton FL
Stephen H. Woltz - Boca Raton FL
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G08B 522
US Classification:
34082544
Abstract:
In a selective call radio paging device, a plurality of alerts are generated in response to the decoding of a message having an address corresponding to the address assigned to the pager. A specific alert envelope waveform is generated and drives an alerting device of a first type (e. g. , a transducer). Inverting means is provided to invert the envelope and cause a second alerting device (e. g. , visual) to be activated in a manner complementary to the first. Thus, alerting devices are not operated concurrently, and peak loads on a resident power source are avoided.

Pager Receiver Having A Common Timer Circuit For Both Sequential Lock-Out And Out-Of-Range

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US Patent:
49280864, May 22, 1990
Filed:
Jan 30, 1989
Appl. No.:
7/302876
Inventors:
George Drapac - Boca Raton FL
Walter J. Grandfield - Lake Worth FL
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H04Q 702
H04B 700
US Classification:
340825440
Abstract:
A pager receiver includes at least one lock-out circuit, an out-of range circuit, and a single timer coupled to the lock-out and out-of range circuits and responsive to timing signals generated by the pager for generating an initiated one of either the lock-out timer interval or out-of range time interval. Each lock-out circuit of the pager receiver corresponds to an address function programmed therein and is activated by the function detect signal generated in response to the initial decoding of the corresponding address function to initiate the generation of the lock-out time interval by the single timer and to inhibit the corresponding alert annunciation from responding to subsequently generated function detect signals corresponding thereto for the duration of the lock-out time interval. The single timer is also initiated to generate the out-of-range time interval at the generation of each sync pulse timing signal by the pager receiver, but only in the absence of an activated lock-out circuit. Accordingly, the single timer is disabled from initiating the generation of the out-of-range time interval for the duration of an initiated lock-out time interval.

Bit Synchronizer

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US Patent:
51114860, May 5, 1992
Filed:
Mar 15, 1989
Appl. No.:
7/324277
Inventors:
Mark L. Oliboni - Boynton Beach FL
Stephen H. Woltz - Boca Raton FL
George A. Drapac - Boca Raton FL
Walter L. Davis - Coral Springs FL
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H04L 710
US Classification:
375120
Abstract:
A paging receiver capable of bit synchronizing to one of two data rates. The receiver has a digital phase locked loop integrated onto a single integrated circuit clocked by a single frequency crystal. The paging receiver receives and synchronizes to a POCSAG signal which may be transmitted at either 512 bits per second or 1200 bits per second. The digital phase locked loop bit synchronizes to either data rate using a single crystal frequency of 76. 8 kHz. The data rate is selected by a bit in the code paging receiver's code plug. The digital phase locked loop is constructed to have a substantially constant frequency to bandwidth ratio at both data rates.
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George A Drapac from Cleveland, TN, age ~75 Get Report