Geoffrey D Cheren

20060083268, Apr 20, 2006

Oct 14, 2004

10/965503

David Holaday - Cornelius OR, US
Geoffrey Cheren - Beaverton OR, US

H04J 3/06

370509000

A method and apparatus for processing packetized data spanning multiple clock cycles includes at least one comparator, for comparing a present clock cycle count to a reference clock cycle count, wherein the reference clock cycle values may be anywhere within the packet and may be non-contiguous with other reference clock cycle values. At least one word recognizer, compares a presently clocked word to a reference word, and an output circuit provides an indication of a favorable word comparison that occurred in response to a favorable clock cycle count comparison.

20180183412, Jun 28, 2018

Dec 28, 2016

15/392790

- BEAVERTON OR, US
GEOFFREY D. CHEREN - BEAVERTON OR, US
BRETT TREVOR - TIGARD OR, US

H03K 3/012
G11C 7/10

A device has a digital-to-analog converter to convert waveform data into analog waveforms, a waveform memory to store stored waveform data, an external waveform interface to receive real-time waveform data from an external device, a waveform multiplexer connected to the digital-to-analog converter to select between the first memory and the external waveform interface, a sequencer to receive and execute instructions to identify and access waveform data to drive the digital-to-analog converter, a sequencer instruction memory to provide stored instructions to the sequencer, an external instruction interface to receive real-time instructions for the sequencer, and a sequencer multiplexer to select between the sequencer instruction memory and the external instruction interface connected to the sequencer. A method of controlling a waveform generator includes selecting a mode of operation, where the mode of operation is selected from streaming waveform data, real-time waveform memory updates, real-time sequencer instructions, real-time sequencer instruction updates, and real-time sequencer flow control.

20160065221, Mar 3, 2016

Dec 19, 2014

14/577952

- Beaverton OR, US
Geoffrey D. Cheren - Beaverton OR, US

H03L 7/083
H03M 1/10
H03M 1/66

A system and method synchronizes multi-AWG system, where such systems are of a type having a master arbitrary waveform generator (AWG), one or more slave AWGs, and a sync hub having a sync controller and sync phase detector. The method operates by receiving at the sync hub a divided down clock (SystemRefClock) signal from a master arbitrary waveform generator (AWG). The method then derives a clock signal (SystemClock) from the SystemRefClock signal received from the master AWG and outputs the SystemClock signal to the master AWG and to the one or more slave AWGs Finally, the SystemClock signal is used to clock a synchronous trigger for the master AWG and one or more slave AWGs to play a waveform. In one aspect, the synchronous trigger includes AlignmentFiducial and Run signals to effect trigger and play commands.