Geary L Leger

58056327, Sep 8, 1998

Nov 19, 1992

7/979573

Geary L. Leger - Fremont CA

Cirrus Logic, Inc. - Fremont CA

H04B 166

375122

The invention doubles the bit rate for a given media bandwidth as compared to, for example, Manchester encoding. It is applicable to serial transmission or storage of digital data. An arbitrary NRZ data stream is first encoded by a pre-encoding method, such as Manchester, that combines clock and data to represent a single NRZ bit in one clock cycle. A toggle flip flop then re-encodes the pre-encoded waveform, thus generating a double toggle (DT) encoded waveform, which spreads the spectral energy over a larger bandwidth and encodes two NRZ data bits within one transmission clock cycle. In the case of Manchester pre-encoding, data is decoded by determining if there are transitions nearly synchronous with an edge of the recovered clock. For other pre-encoding methods, decoded data is determined by the length of the transition period and the edge polarity of the recovered clock at the leading edge of the transition within the DT encoded waveform. DC offset is reduced by substitution within and inversion of the DT encoded waveform.

58386610, Nov 17, 1998

Mar 27, 1996

8/623260

Geary Leger - Fremont CA
Bhoopal R. Benjaram - Sunnyvale CA
Peter R. Carpenter - Watsonville CA

Cirrus Logic, Inc. - Fremont CA

H04J 116
H04J 314

370229

A method and arrangement for shutting off a receive channel in a data communications system to prevent accidental or intentional overwhelming of the memory of the system such as that caused by a continuous burst of short frame data. The data frames received are monitored by a shutoff counter as they are received on one of the channels of a serial input/output (I/O) device. When the shutoff count is reached, the receive channel will be shut off. The current value of the shutoff counter is compared to a value stored in a warning register. Before reaching the shutoff count, a warning is generated when the current shutoff counter value reaches the warning register value.

57322864, Mar 24, 1998

Aug 10, 1995

8/513463

Geary L. Leger - Fremont CA

Cirrus Logic, Inc. - Fremont CA

G06F 0506

395877

An apparatus and method for efficiently receiving a long string of short data packets. Storing a long string of short data packets received from external devices can be inefficient in terms of system resources such as system memory and CPU time. In the preferred embodiment of the present invention, both the number of data packets in the FIFO buffer and the demand of system memory are monitored. A FIFO buffer of at least 32 bytes deep and having a packet-based threshold is implemented to monitor the number of data packets in the FIFO buffer. When the number of data packets in the FIFO buffer is equal to or exceeds the threshold and there is a predetermined number of free buffer memory available, data is transferred from the FIFO buffer to system memory. The number of data packets transferred from the FIFO buffer is also monitored to control the amount of data transfer. Any data stuck inside the FIFO buffer for a predetermined period of time is automatically unloaded.

57713561, Jun 23, 1998

Jan 4, 1995

8/368562

Geary Leger - Fremont CA
Sriraman Chari - Fremont CA

Cirrus Logic, Inc. - Fremont CA

G06F 1300
G06F 1314

39520063

This invention provides efficient and flexible data transfer management for a First-In First-Out (FIFO) buffer connects to a system bus and implements multiple data thresholds (e. g. , two). Data transfer by the FIFO is controlled by either casually or more aggressively acquiring the system bus based on the amount of data inside the FIFO and on the state of the system bus. By balancing the bus activity level against the FIFO data level, bus access is facilitated at times when the bus has lower activity. This makes the FIFO less obtrusive when moving data across the bus. As a result, the bus is used more efficiently. The system bus is casually acquired when the FIFO data level reaches a soft threshold and the system bus is idle. Casual control of the system bus is relinquished when request from another device sharing the bus is received and a predetermined amount of data has been transferred. On the other hand, the system bus is more aggressively acquired when the FIFO data level reaches a hard threshold.

54467659, Aug 29, 1995

Aug 17, 1994

8/292629

Geary L. Leger - Fremont CA

Cirrus Logic, Inc. - Fremont CA

H04L 702

375359

The invention doubles the bit rate for a given media bandwidth as compared to, for example, Manchester encoding. It is applicable to serial transmission or storage of digital data. An arbitrary NRZ data stream is first encoded by a pre-encoding method, such as Manchester, that combines clock and data to represent a single NRZ bit in one clock cycle. A toggle flip flop then re-encodes the pre-encoded waveform, thus generating a double toggle (DT) encoded waveform, which spreads the spectral energy over a larger bandwidth and encodes two NRZ data bits within one transmission clock cycle. In the case of Manchester pre-encoding, data is decoded by determining if there are transitions nearly synchronous with an edge of the recovered clock. For other pre-encoding methods, decoded data is determined by the length of the transition period and the edge polarity of the recovered clock at the leading edge of the transition within the DT encoded waveform. DC offset is reduced by substitution within and inversion of the DT encoded waveform.

57817995, Jul 14, 1998

Sep 29, 1995

8/536729

Geary Leger - Fremont CA
Bhoopal R. Benjaram - Sunnyvale CA
Peter R. Carpenter - Watsonville CA
Gary L. Schaps - Fremont CA
John Andrew Wishneusky - Boston MA

Cirrus Logic, Inc. - Fremont CA

G06F 1502

395842

A method and arrangement for performing direct memory access in a computer system having multi-channel direct memory access (DMA) is provided with a host computer having a main memory and a processor that runs software, a system interface bus coupling the host computer and the main memory, and multiple DMA controllers, on separate chips, coupled to the system interface bus. These multiple DMA controllers provide the system with multiple input/output (I/O) channels. A common buffer pool having a plurality of buffers is accessible to each of the multiple channels for buffering data transferred to or from the host computer. A status queue is also provided, with each entry in the status queue indicating whether a corresponding buffer from the common pool of buffers is a free buffer available for use by one of the DMA channels in a DMA transaction. The status queue is searched for an entry in the status queue which indicates whether its corresponding buffer is a free buffer, when a DMA transaction is to occur over one of the DMA channels. When a free buffer is found, the entry in the status queue and the free buffer are claimed by the DMA channel.

52356990, Aug 10, 1993

Feb 1, 1991

7/649771

James M. Shaffer - Boise ID
Karl H. Mauritz - Eagle ID
Henry D. Gerdes - Boise ID
Geary L. Leger - Fremont CA

Micron Technology, Inc. - Boise ID

G06F 1300

395550

A circuit that controls, calibrates and monitors critical timing parameters in a computer system or network to prevent loss of, or inaccurate data, when transferring this data.

57650233, Jun 9, 1998

Sep 29, 1995

8/536732

Geary L. Leger - Fremont CA
Bhoopal R. Benjaram - Sunnyvale CA
Peter R. Carpenter - Watsonville CA
Gary L. Schaps - Fremont CA
John Andrew Wishneusky - Bolton MA

Cirrus Logic, Inc. - Fremont CA

G06F 1540

395842

A method and arrangement for performing direct memory access in a computer system having multi-channel direct memory access (DMA) is provided with a host computer having a main memory and a processor that runs software, a system interface bus coupling the host computer and the main memory, and a multi-channel DMA controller arrangement coupled to the system interface bus and having multiple input/output (I/O) channels. A common buffer pool having a plurality of buffers is accessible to each of the multiple channels for buffering data transferred to or from the host computer. A status queue is also provided, with each entry in the status queue indicating whether a corresponding buffer from the common pool of buffers is a free buffer available for use by one of the DMA channels in a DMA transaction. The status queue is searched for an entry in the status queue which indicates whether its corresponding buffer is a free buffer, when a DMA transaction is to occur over one of the DMA channels. When a free buffer is found, the entry in the status queue and the free buffer are claimed by the DMA channel.