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Gautam V Thakar

from Plano, TX
Age ~73

Gautam Thakar Phones & Addresses

  • 412 Ruidosa Cir, Plano, TX 75023
  • Dallas, TX
  • Planada, CA
  • La Mesa, CA

Publications

Us Patents

Polysilicon Processing Using An Anti-Reflective Dual Layer Hardmask For 193 Nm Lithography

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US Patent:
6803661, Oct 12, 2004
Filed:
Aug 21, 2003
Appl. No.:
10/645032
Inventors:
Gautam V. Thakar - Plano TX
Reima T. Laaksonen - Dallas TX
Cameron Gross - Allen TX
Eric A. Joseph - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2348
US Classification:
257758, 257759, 257760
Abstract:
A lithographic method of forming submicron polysilicon features on a semiconductor substrate, including the steps of coating said substrate with an anti-reflective coating (ARC) comprising two layers having matched indices of refraction (n) and extinction coefficient (k) selected to reduce reflection to less than 1% with 193 nm wavelength exposure. The ARC is subsequently patterned to serve as an etch hardmask. Preferably the ARC mask consists of a first layer of between 300 and 1500 angstroms of silicon rich silicon nitride having an extinction coefficient of from 0. 77 to 1. 07, and a second layer of between 170 and 320 angstroms of silicon oxynitride having an extinction coefficient of about 0. 32.

Polysilicon Processing Using An Anti-Reflective Dual Layer Hardmask For 193 Nm Lithography

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US Patent:
20030040179, Feb 27, 2003
Filed:
Aug 24, 2001
Appl. No.:
09/939259
Inventors:
Gautam Thakar - Plano TX,
Reima Laaksonen - Dallas TX,
Cameron Gross - Allen TX,
Eric Joseph - Dallas TX,
International Classification:
H01L021/302
H01L021/461
US Classification:
438/689000
Abstract:
A lithographic method of forming submicron polysilicon features on a semiconductor substrate, including the steps of coating said substrate with an anti-reflective coating (ARC) comprising two layers having matched indices of refraction (n) and extinction coefficient (k) selected to reduce reflection to less than 1% with 193 nm wavelength exposure. The ARC is subsequently patterned to serve as an etch hardmask. Preferably the ARC mask consists of a first layer of between 300 and 1500 angstroms of silicon rich silicon nitride having an extinction coefficient of from 0.77 to 1.07, and a second layer of between 170 and 320 angstroms of silicon oxynitride having an extinction coefficient of about 0.32.

Semiconductor Structure And Method Of Fabrication

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US Patent:
20040191999, Sep 30, 2004
Filed:
Mar 24, 2003
Appl. No.:
10/396139
Inventors:
Pr Chidambaram - Richardson TX,
Srinivasan Chakravarthi - Richardson TX,
Gautam Thakar - Plano TX,
Toan Tran - Rowlett TX,
Assignee:
Texas Instruments Incroporated
International Classification:
H01L021/336
US Classification:
438/305000
Abstract:
Fabricating a semiconductor includes forming a conductive layer outwardly from a surface of a substrate. A mask layer comprising a hard mask is deposited outwardly from the conductive layer to pattern the conductive layer to form a gate stack. The conductive layer is etched to remove the conductive layer from the surface of the substrate and to form the gate stack, where the mask layer is disposed outwardly from the gate stack. Ions are implanted outwardly from the surface of the substrate, where the mask layer prevents at least a portion of the ions from penetrating the gate stack while penetrating the substrate.
Gautam V Thakar from Plano, TX, age ~73 Get Report