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Gautam A Dusija

from Burlingame, CA
Age ~41
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Also known as:
Gautam Ashok Dusija, Dusija Gautam, Gautam A
Phone and address:
2720 Trousdale Dr, Burlingame, CA 94010
Related to:
Dusija Gautam, 62
Connected to:
Mitzi K Dusin, 53Thomas L Dusin, 73Dan L Dusing, 83Michelle D Dusing, 39Shelly M Dusing, 51Kelly L Duska, 56Theresa G Duska, 76Waller Duska, 49Clifford R Duske, 65Frederick J Duske, 58

Gautam Dusija Phones & Addresses

  • 2720 Trousdale Dr, Burlingame, CA 94010
  • Fremont, CA
  • 460 4Th St, San Jose, CA 95112 (408) 279-4684
  • Milpitas, CA
  • 460 S 4Th St APT 13, San Jose, CA 95112 (408) 279-4684

Publications

Us Patents

Non-Volatile Memory And Method With Post-Write Read And Adaptive Re-Write To Manage Errors

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US Patent:
8423866, Apr 16, 2013
Filed:
Dec 18, 2009
Appl. No.:
12/642728
Inventors:
Gautam Ashok Dusija - Milpitas CA, US
Jian Chen - Menlo Park CA, US
Chris Avila - Sunnyvale CA, US
Jianmin Huang - Sunnyvale CA, US
Lee M. Gavens - Milpitas CA, US
Assignee:
SanDisk Technologies, Inc. - Plano TX
International Classification:
G06F 11/00
US Classification:
714773, 714 624, 711103
Abstract:
Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. Input data is written and staged in the first portion before being copied to the second portion. An error management provides checking the quality of the copied data for excessive error bits. The copying and checking are repeated on a different location in the second portion until either a predetermined quality is satisfied or the number or repeats exceeds a predetermined limit. The error management is not started when a memory is new with little or no errors, but started after the memory has aged to a predetermined amount as determined by the number of erase/program cycling its has experienced.

Non-Volatile Memory And Method With Atomic Program Sequence And Write Abort Detection

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US Patent:
20110149651, Jun 23, 2011
Filed:
Dec 18, 2009
Appl. No.:
12/642740
Inventors:
Sergey Anatolievich Gorobets - Edinburgh, GB
Gautam Ashok Dusija - Milpitas CA, US
International Classification:
G11C 16/04
G11C 16/16
G11C 16/06
US Classification:
36518503, 36518511, 36518533, 36518509
Abstract:
A program operation in a non-volatile memory is segmented at predefined junctures into smaller segments for execution over different times. The predefined junctures are such that they allow unambiguous identification when restarting the operation in a next segment so that the operation can continue without having to restart from the very beginning of the operation. This is accomplished by requiring the programming sequence of each segment to be atomic, that is, to only terminate at a predetermined type of programming step. In a next segment, the terminating programming step is identified by detecting a predetermined pattern of ECC errors across a group of programmed wordlines.

Balanced Performance For On-Chip Folding Of Non-Volatile Memories

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US Patent:
20120311244, Dec 6, 2012
Filed:
Jun 8, 2012
Appl. No.:
13/491879
Inventors:
Yichao Huang - San Jose CA, US
Jianmin Huang - Sunnyvale CA, US
Gautam Ashok Dusija - Milpitas CA, US
Oleg Kragel - Minsk, BY
International Classification:
G06F 12/00
US Classification:
711103, 711E12008
Abstract:
A non-volatile memory system receives and stores host data. As the memory system receives host data, it initially writes the data in a binary format and then subsequently performs an on-chip folding operation on the data, storing the data in a multi-state format. The memory system interleaves the phases of the folding operations so that performance is made more uniform across allocation units, where the host stores data according to allocation units. The memory system also can perform the binary and subsequent on-chip folding operations on multiple memory planes in parallel, where the controller also balances the operations so that performance is made more uniform between planes with respect to allocation units as the data is received from the host. To further maintain performance, the memory system uses a free block list having a reserve portion that is only accessible for a specified set of commands.

Auxiliary Card Initialization Routine

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US Patent:
20130166893, Jun 27, 2013
Filed:
Dec 23, 2011
Appl. No.:
13/336223
Inventors:
Gautam A. Dusija - San Jose CA, US
Jianmin Huang - Sunnyvale CA, US
Chris Avila - Sunnvale CA, US
Assignee:
SANDISK TECHNOLOGIES INC. - Plano TX
International Classification:
G06F 9/445
US Classification:
713 2
Abstract:
A memory system or flash card may be initialized from a protected block of flash memory as a backup process. If there is an error during regular card initialization and the firmware for the card cannot be loaded, the card may be inaccessible to a user. Booting with a protected block of memory may be used to load a different version of the firmware that can still initialize the card despite the error from loading the other firmware.

Enhanced Write Abort Management In Flash Memory

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US Patent:
20130205066, Aug 8, 2013
Filed:
Feb 3, 2012
Appl. No.:
13/365595
Inventors:
Gautam A. Dusija - San Jose CA, US
Jianmin Huang - Sunnyvale CA, US
Chris Avila - Saratoga CA, US
Assignee:
SANDISK TECHNOLOGIES INC. - Plano TX
International Classification:
G06F 12/00
US Classification:
711103
Abstract:
A memory system or flash card may include safe zone blocks where data is written in case of an error condition, such as a write abort. The system may utilize predetermined risk zones when selecting the data that is written to the safe zone blocks. For example, data written to a lower page may be one example of data that is a predetermined risk. Upon receiving a write command, the data that is written to a lower page may be written to a safe zone either in parallel or after the write operation.

Write Abort Recovery Through Intermediate State Shifting

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US Patent:
20130219107, Aug 22, 2013
Filed:
Feb 21, 2012
Appl. No.:
13/401494
Inventors:
Dana Lee - Saratoga CA, US
Pao-Ling Koh - Fremont CA, US
Jianmin Huang - Sunnyvale CA, US
Gautam A. Dusija - San Jose CA, US
Assignee:
SANDISK TECHNOLOGIES INC. - Plano TX
International Classification:
G06F 12/02
US Classification:
711103, 711E12008
Abstract:
A memory system or flash card may include a multi-level cell block with multiple states. Before the upper page is written, an intermediate state may be shifted to prevent or minimize overlapping of the states from the corresponding lower page. A write abort during the writing of the upper page will not result in a loss of data from the corresponding lower page.

Experience Count Dependent Program Algorithm For Flash Memory

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US Patent:
20140029342, Jan 30, 2014
Filed:
Jul 27, 2012
Appl. No.:
13/560896
Inventors:
Jianmin Huang - San Carlos CA, US
Kulachet Tanpairoj - Santa Clara CA, US
Chris Nga Yee Avila - Saratoga CA, US
Gautam Ahok Dusija - Milpitas CA, US
Assignee:
SanDisk Technologies Inc. - Plano TX
International Classification:
G11C 16/04
US Classification:
36518512, 36518511, 36518518, 36518529
Abstract:
In a non-volatile memory device, the parameters used in write and erase operation are varied based upon device age. For example, in a programming operation using a staircase waveform, the amplitude of the initial pulse can be adjusted based upon the number of erase-program cycles (hot count) of the block containing the selected physical page for the write. This arrangement can preserve performance for relatively fresh devices, while extending life as a devices ages by using gentler waveforms as the device ages.

Erased Page Confirmation In Multilevel Memory

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US Patent:
20140075252, Mar 13, 2014
Filed:
Mar 4, 2013
Appl. No.:
13/784693
Inventors:
Jianmin Huang - San Carlos CA, US
Chris Nga Yee Avila - Saratoga CA, US
Dana Lee - Saratoga CA, US
Gautam Ashok Dusija - Milpitas CA, US
Assignee:
SanDisk Technologies Inc. - Plano TX
International Classification:
G11C 29/50
US Classification:
714721
Abstract:
In a multi-level cell memory array, a flag that indicates that a logical page is unwritten is subject to a two-step verification. In a first verification step, the logical page is read, and ECC decoding is applied. If the first verification step indicates that the logical page is unwritten, then a second verification step counts the number of cells that are not in an unwritten condition.
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Gautam A Dusija from Burlingame, CA, age ~41 Get Report